BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 117)

PDI Description
Slave Controller – IP Core for Xilinx FPGAs III-105
10.5.2 Configuration
The OPB interface has PDI type 0x80 in the PDI control register 0x0140. The OPB bus clock speed is
configurable in the OPB PDI configuration dialog. If the EtherCAT IP Core is used in a Xilinx EDK
design, the address range can be specified there and the reset polarity can be configured to be active
high.
OPB Bus Clock Multiplier
The OPB clock frequency is a multiple of 25 MHz:
OPB clock frequency = N * 25 MHz (N=1...31)
The maximum clock speed depends on the FPGA and the synthesis. The rising edge of OPB clock
has to be synchronous with the rising edge of CLK25 of the EtherCAT IP Core.
OPB Bus Data Width
The width of the OPB data bus can be W = 1, 2, or 4 Bytes. Select W = 4 Bytes for the Xilinx
Microblaze processor.
NOTE: Independent of the OPB bus data width, DBUS width remains [0:31] and BE width remains [0:3]. Use bits
[0:7] or [0:15] for DBUS, and [0] or [0:1] for BE respectively, if width is reduced.
Address Range (C_BASEADDR and C_HIGHADDR)
The address range of the EtherCAT IP Core OPB slave is defined with two VHDL generics
C_BASEADDR (holding the base address) and C_HIGHADDR (containing the end address). The
address range of the EtherCAT IP core should span at least 64 Kbyte (e.g., C_BASEADDR =
0x00010000 and C_HIGHADDR=0x0001FFFF). A larger address range results in less address
decoding logic.
RESET Polarity (RESET_POL_ACT_HIGH)
The Xilinx EDK assumes the OPB reset signal to be active high, so the polarity of the EtherCAT IP
Core can be configured to be active high with this generic. A value of 0 means active low, a value of 1
means active high. The reset polarity will be automatically set to active high by the configuration tool, if
the OPB PDI is selected.
10.5.3 Byte Enable (BE)
The Byte Enable signal specifies active byte lanes for an access. These values are allowed for
BE[0:3]: 0000, 0001, 0010, 0100, 1000, 0011, 1100, and 1111.