6 tested fpga/designflow combinations, Tested fpga/designflow combinations, Table 3: tested fpga/designflow combinations – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual
Page 17
Overview
Slave Controller
– IP Core for Xilinx FPGAs
III-5
1.6
Tested FPGA/Designflow combinations
The EtherCAT IP Core has been synthesized successfully with different ISE/EDK versions and FPGA
families. Table 3 lists combinations of FPGA devices and design tools versions which have been
synthesized or even tested in real hardware. This list does not claim to be complete, it just illustrates
that the EtherCAT IP Core is designed to comply with a broad spectrum of FPGAs.
Table 3: Tested FPGA/Designflow combinations
IP Core Family
Device
Designflow
Test
Used Example
Designs
2.04e
Spartan-3E
XC3S1200E
ISE 14.7
Synthesis
Spartan-6
XC6SLX150T
ISE 14.7
EDK 14.7
Hardware LX150T DIGI & PLB
Artix-7
XC7A100T
ISE 14.7
Synthesis
Kintex-7
XC7K70T
ISE 14.7
Synthesis
Virtex-4
XC4VLX25
ISE 14.7
Synthesis
Virtex-5
XC5VLX30
ISE 14.7
Synthesis
Virtex-6
XC6VLX75T
ISE 14.7
Synthesis
Virtex-7
XC7VX330T
ISE 14.7
Synthesis
Kintex
UltraScale
XCKU035
Vivado
2014.3
Synthesis
Virtex
UltraScale
XCVU080
Vivado
2014.3
Synthesis
Zynq 7020
XC7Z020
ISE 14.7
Synthesis
NOTE: Synthesis test means XST synthesis, implementation and programming file generation. Hardware test
means the design was operational on hardware.
Refer to the Hardware Data Sheet Section III Addendum available at the Beckhoff homepage
for latest updates regarding device support, design flow compatibility, and
known issues.