BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 119)

PDI Description
Slave Controller – IP Core for Xilinx FPGAs III-107
CLK
OPB
ABUS ADR
RNW
SL_XFERACK
SL_DBUS DATA
t
Read
CS
t
Clk
SL_TOUTSUP
BE BE
Figure 57: OPB Read Access
CLK
OPB
ABUS ADR
RNW
SL_XFERACK
DBUS
t
Write
CS
t
Clk
SL_TOUTSUP
DATA
BE BE
Figure 58: OPB Write Access