BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 64)

FPGA Resource Consumption
III-52 Slave Controller – IP Core for Xilinx FPGAs
The EtherCAT IP core resource consumption figures for typical EtherCAT devices are based on
EtherCAT IP Core for Xilinx FPGAs Version 2.04a, Xilinx ISE 12.4, and Xilinx Spartan-3E or Spartan-6
devices.
Table 16: EtherCAT IP Core configuration for typical EtherCAT Devices
EtherCAT Device SM FMMU DPRAM
[kByte]
PDI DC Register
preset
IO 2 2 1 32 Bit Digital I/O - Small
Frequency Inverter 4 3 1 SPI - Large
Encoder 4 3 1 SPI 32 bit Large
Fieldbus Gateway 4 3 4 16 Bit µC - Large
Servo Drive 4 3 4 16 Bit µC 32 bit Large
NOTE: Register preset medium and large including MII Management Interface. All devices have 2 MII ports, DC is
32 bit wide.
Table 17: EtherCAT IP Core resource consumption for typical EtherCAT Devices
EtherCAT Device Spartan-3E Spartan-6
Slices Reg. Log.
LUT4
Slices Reg. Log.
LUT6
IO 4,200 3,900 6,200 1,900 3,900 5,000
Frequency Inverter 6,200 5,200 9,000 2,300 5,300 7,000
Encoder 9,000 8,100 12,400 2,500 8,100 9,800
Fieldbus Gateway 6,100 5,100 8,900 2,400 5,100 6,900
Servo Drive 8,900 8,000 12,200 2,500 8,000 9,800