3 extended esc features in user ram, Extended esc features in user ram, 0x0f80:0x0fff) – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual
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Features and Registers
Slave Controller
– IP Core for Xilinx FPGAs
III-19
2.3
Extended ESC Features in User RAM
Table 11: Extended ESC Features (Reset values of User RAM
– 0x0F80:0x0FFF)
Bit
Description
small
medium
large
7:0
Number of extended feature bits
142
IP Core extended features:
0:
Not available
1:
Available
c:
Configurable
8
Extended DL Control Register (0x0102:0x0103)
1
1
1
9
AL Status Code Register (0x0134:0x0135)
c
1
1
10
ECAT Interrupt Mask (0x0200:0x0201)
c
c
1
11
Configured Station Alias (0x0012:0x0013)
1
1
1
12
General Purpose Inputs (0x0F18:0x0F1F)
c
c
c
13
General Purpose Outputs (0x0F10:0x0F17)
c
c
c
14
AL Event Mask (0x0204:0x0207)
c
1
1
15
Physical Read/Write Offset (0x0108:0x0109)
c
c
1
16
Watchdog divider writeable (0x0400:0x04001) and
Watchdog PDI (0x0410:0x0f11)
c
1
1
17
Watchdog counters (0x0442:0x0443)
c
c
1
18
Write Protection (0x0020:0x0031)
c
c
1
19
Reset (0x0040:0x0041)
c
c
c
20
Reserved
0
0
0
21
DC SyncManager Event Times (0x09F0:0x09FF)
c
c
1
22
ECAT Processing Unit/PDI Error Counter
(0x030C:0x030D)
c
c
1
23
EEPROM Size configurable (0x0502.7):
0:
EEPROM Size fixed to sizes up to 16 Kbit
1:
EEPROM Size configurable
1
1
1
24
Reserved
1
1
1
25
Reserved
0
0
0
26
Reserved
0
0
0
27
Lost Link Counter (0x0310:0x0313)
c
1
1
28
MII Management Interface (0x0510:0x0515)
c
c
c
29
Enhanced Link Detection MII
c
c
c
30
Enhanced Link Detection EBUS
0
0
0
31
Run LED (DEV_STATE LED)
c
c
c
32
Link/Activity LED
1
1
1
33
Reserved
0
0
0
34
Reserved
1
1
1
35
Reserved
1
1
1
36
Reserved
0
0
0
37
Reserved
1
1
1
38
DC Time loop control assigned to PDI
c
c
c
39
Link detection and configuration by MI
c
c
c
40
MI control by PDI possible
1
1
1
41
Automatic TX shift
c
c
c
42
EEPROM emulation by µController
c
c
c
43
Reserved
0
0
0