BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e - Manual (Page 48)

IP Core Configuration
III-36 Slave Controller – IP Core for Xilinx FPGAs
5.1.4 Feature Details tab
Figure 16: Feature Details tab
Base Feature Set (current feature set)
Depending on the IP Core functionality that should be implemented and the available resources (LEs)
in the FPGA, the internal features can be chosen. Three feature presets are available: small, medium
and large. Based upon these presets, additional functions can be enabled on this tab.
Read/Write Offset
Physical Read/Write Offset (0x00108:0x0109) is available if checked.
Write Protection
Register write protection and ESC write protection (0x0020:0x0031) are available if checked.
AL Status Code Register
AL Status Code register (0x0134:0x0135) is available if checked.
Extended Watchdog
Watchdog Divider (0x0400:0x0401) is configurable and PDI Watchdog (0x0410:0x0411, and
0x0100.1) is available if checked.
AL Event Mask Register
AL Event Mask register (0x0204:0x0207) is available if checked.
Watchdog Counter
Watchdog Counters (0x0442:0x0443) are available if checked. Watchdog Counter PDI is only used if
Extended Watchdog feature is selected.
System Time PDI controlled
Distributed Clocks Time Loop Control Unit is controlled by PDI (µController) if selected. EtherCAT
access is not possible. Used for synchronization of secondary EtherCAT busses.