FIGURES
III-X
Slave Controller
– IP Core for Xilinx FPGAs
Figure 1: EtherCAT IP Core Block Diagram ............................................................................................ 1
Figure 2: Frame Processing .................................................................................................................... 2
Figure 3: Design flow ............................................................................................................................... 8
Figure 4: Files installed with EtherCAT IP Core setup .......................................................................... 21
Figure 5: IPCore_Config Open Menu .................................................................................................... 26
Figure 6: IP Core generation successful ............................................................................................... 26
Figure 7: EDK
– Overview ..................................................................................................................... 28
Figure 8: EDK
– Configuration of IP Core ............................................................................................. 28
Figure 9: EDK
– Configuration Dialog ................................................................................................... 29
Figure 10: EDK
– System Assembly View, Addresses tab ................................................................... 29
Figure 11: EDK
– System Assembly View, Ports tab ............................................................................ 30
Figure 12: EtherCAT IP Core Configuration Interface ........................................................................... 32
Figure 13: Product ID tab ...................................................................................................................... 33
Figure 14: Physical Layer tab ................................................................................................................ 34
Figure 15: Internal Functions tab ........................................................................................................... 35
Figure 16: Feature Details tab ............................................................................................................... 36
Figure 17: Available PDI Interfaces ....................................................................................................... 38
Figure 18: Register Process Data Interface .......................................................................................... 39
Figure 19: Register PDI
– Digital I/O Configuration............................................................................... 40
Figure 20: Register PDI
– µC-Configuration.......................................................................................... 41
Figure 21: Register PDI
– SPI Configuration ......................................................................................... 42
Figure 22: Register PDI
– PLB Interface Configuration ........................................................................ 43
Figure 23: Register PDI
– OPB Interface Configuration ........................................................................ 44
Figure 24: EtherCAT IP Core clock source (MII) ................................................................................... 53
Figure 25: EtherCAT IP Core clock source (RMII) ................................................................................ 54
Figure 26: PHY management Interface signals..................................................................................... 66
Figure 27: Example schematic with two individual MII management interfaces ................................... 67
Figure 28: MII Interface signals ............................................................................................................. 69
Figure 29: MII TX Timing Diagram ........................................................................................................ 70
Figure 30: MII timing RX signals............................................................................................................ 71
Figure 31: MII example schematic......................................................................................................... 72
Figure 32: RMII Interface signals........................................................................................................... 73
Figure 33: RMII example schematic ...................................................................................................... 74
Figure 34: IP core digital I/O signals ..................................................................................................... 76
Figure 35: Digital Output Principle Schematic ....................................................................................... 78
Figure 36: Digital Input: Input data sampled at SOF, I/O can be read in the same frame .................... 80
Figure 37: Digital Input: Input data sampled with LATCH_IN ................................................................ 80
Figure 38: Digital Output timing ............................................................................................................. 80
Figure 39: OUT_ENA timing .................................................................................................................. 80
Figure 40: SPI master and slave interconnection.................................................................................. 81
Figure 41: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK) .... 87
Figure 42: SPI read access (2 byte addressing, 1 byte read data) with Wait State byte ...................... 88
Figure 43: SPI read access (2 byte addressing, 2 byte read data) with Wait State byte ...................... 89
Figure 44: SPI write access (2 byte addressing, 1 byte write data) ...................................................... 90
Figure 45: SPI write access (3 byte addressing, 1 byte write data) ...................................................... 91
Figure 46: µController interconnection .................................................................................................. 92
Figure 47: Connection with 16 bit µControllers without byte addressing .............................................. 94
Figure 48: Connection with 8 bit µControllers (BHE and DATA[15:8] should not be left open) ............ 95
Figure 49: Read access (without preceding write access) .................................................................... 98
Figure 50: Write access (write after rising edge nWR, without preceding write access) ...................... 98
Figure 51: Sequence of two write accesses and a read access ........................................................... 99
Figure 52: Write access (write after falling edge nWR) ......................................................................... 99
Figure 53: PLB signals ........................................................................................................................ 100
Figure 54: PLB Read Access .............................................................................................................. 103
Figure 55: PLB Write Access ............................................................................................................... 103
Figure 56: OPB signals ........................................................................................................................ 104
Figure 57: OPB Read Access .............................................................................................................. 107
Figure 58: OPB Write Access .............................................................................................................. 107
Figure 59: Distributed Clocks signals .................................................................................................. 108
Figure 60: LatchSignal timing .............................................................................................................. 108
