1 no interface and general purpose i/o, Figure 18: register process data interface – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual

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1 no interface and general purpose i/o, Figure 18: register process data interface | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual | Page 51 / 126 1 no interface and general purpose i/o, Figure 18: register process data interface | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual | Page 51 / 126
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