6 on-chip peripheral bus (opb) configuration, Figure 23: register pdi, Opb interface configuration – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual

6 on-chip peripheral bus (opb) configuration, Figure 23: register pdi, Opb interface configuration | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual | Page 56 / 126