Comtech EF Data SNM-1001 - Manual (Page 38)

SNM-1001 Network Control Modem Theory of Operation
Rev. 1 4–7
The result is a filtered, digital representation of the received signal. A Costas loop
maintains the phase lock during the message. A phase-lock loop maintains the data clock.
The soft-decision mapper converts the I&Q samples to soft-decision values. The
soft-decision values are then fed to the Viterbi decoder, where error detection and
correction are performed.
The I&Q channels are also used to calculate the AGC and AOC voltages. The AGC and
AOC are fed back to the RF module.
Finally, the data from the output of the Viterbi decoder is descrambled with a 2 15 -1
synchronous descrambler, and routed to the interface card. There also is a summary fault
relay that provides a FORM C output located on the demodulator board.
The data clock phase can be selected from the Interface Utility menu.
Using Digital Signal Processing (DSP) techniques, the demodulator looks for carrier
power in an 8 kHz bandwidth. When a carrier is detected, the DSP calculates the offset
from the nominal frequency. The DSP then zeros out the offset. This occurs during the
CW portion of the preamble sequence. During the second part of the preamble sequence,
the clock phase is recovered. When the unique word is detected, the Demod determines
the ambiguity of the received signal. It then corrects the ambiguity, if necessary, and
starts feeding data to the Viterbi decoder. A delay generator determines when the first bit
of the data packet comes out of the Viterbi decoder, and initiates the synchronous load of
the 2
15 -1 synchronous descrambler. After the descrambler starts the lock, the RR lines are
set to true, denoting that valid data is being received. The demodulator, when locked,
continually monitors the incoming data for the end-of-message marker. When the
end-of-message marker is detected, a delay generator determines when the remaining
data has been flushed out of the modem, and the Lock and RR line is set to false.
Note: The data packet must not be less than 48 bits of data. There is no maximum length
for the data packet.
4.2.3 Viterbi Decoding Theory
The Viterbi decoder is used in open-network applications, typically in Intelsat Business
Service (IBS) or Intermediate Data Rate (IDR) communication systems. The Viterbi
decoder operates in conjunction with the convolutional encoder in the transmit modem.
The Viterbi decoder and convolutional encoder correct the transmission channel errors in
the received data stream.
Figure 4-3 is a block diagram of the Viterbi decoder.