H3C Technologies H3C S9500E Series Switches - Manual (Page 58)

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Done!
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* H3C S9500E BootWare, Version 1.09 *
* *
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Copyright (c) 2004-2009 Hangzhou H3C Technologies Co., Ltd.
Compiled Date : Jul 22 2009
CPU Type : MPC8548E
CPU L1 Cache : 32KB
CPU L2 Cache : 512KB
CPU Clock Speed : 1000MHz
Memory Type : DDR2 SDRAM
Memory Size : 1024MB
Memory Speed : 400MHz
BootWare Size : 4MB
Flash Size : 128MB
cfa0 Size : 247MB
NVRAM Size : 1024KB
BASIC CPLD Version : 001F
EXTEND CPLD Version : 001F
PCB Version : Ver.B
The switch initiates the power-on self-test (POST) and the results are displayed at the console terminal.
Board self testing...........................
Board steady testing... [ PASS ]
Board SlotNo... [ 0 ]
Subcard exist testing... [ PASS ]
DX246 testing... [ PASS ]
PHY88E1111 testing... [ PASS ]
CPLD1 testing... [ PASS ]
CPLD2 testing... [ PASS ]
NS16550 register testing... [ PASS ]
The default switch's Mac address... [00:e0:fc:00:95:12]
CF Card testing... [ PASS ]
BootWare Validating...
Press Ctrl+B to enter extended boot menu...
When the POST is complete, the switch boots the applications. The following information appears on the
terminal screen (only part of the display information is given in this example):
Starting to get the main application file--flash:/switch.bin!
The main application file is self-decompressing...........................
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Done!
System is starting...