Avago Technologies LSI8751D User Manual
Page 183
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5-67
HTH [7:4]
SEL [3:0]
GEN [3:0]
Minimum Time-out
1
(50 MHz Clock)
1. These values will be correct if the CCF bits in the
register are set according to the valid combinations in the bit
description.
GENSF = 0
GENSF = 1
0000
Disabled
Disabled
0001
100
µ
s
1.6 ms
0010
200
µ
s
3.2 ms
0011
400
µ
s
6.4 ms
0100
800
µ
s
12.8 ms
0101
1.6 ms
25.6 ms
0110
3.2 ms
51.2 ms
0111
6.4 ms
102.4 ms
1000
12.8 ms
204.8 ms
1001
25.6 ms
409.6 ms
1010
51.2 ms
819.2 ms
1011
102.4 ms
1.6 s
1100
204.8 ms
3.2 s
1101
409.6 ms
6.4 s
1110
819.2 ms
12.8 s
1111
1.6 s
25.6 s
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