Avago Technologies LSI8751D - Manual (Page 251)

PCI and External Memory Interface Timing Diagrams 7-15
7.4.1 Target Timing
Figure 7.9 through Figure 7.14 describe Target timing.
Figure 7.9 PCI Configuration Register Read
Data Out
Byte Enable
Addr In
t
2
In Out
t
1
t
2
t
1
t
3
t
2
t
1
t
1
t
2
t
2
t
3
t
3
t
2
t
1
t
3
t
2
t
1
CLK
(Driven by System)
FRAME/
(Driven by System)
AD/
(Driven by Master-Addr;
LSI53C875-Data)
C_BE/
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C875-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875)
STOP/
(Driven by LSI53C875)
DEVSEL/
(Driven by LSI53C875)
IDSEL
(Driven by Master)
CMD