Avago Technologies LSI8751D - Manual (Page 297)

LSI53C875/875E PCI to Ultra SCSI I/O Processor A-1
Appendix A
Register Summary
Table A.1 lists the LSI53C875 configuration registers by register name.
Table A.1 Configuration Registers
Register Name Address Read/Write Page
Base Address One (Memory) 0x14 Read/Write 3-19
Base Address Zero (I/O) 0x10 Read/Write 3-19
Bridge Support Extensions (PMCSR_BSE) 0x46 Read Only 3-27
Cache Line Size 0x0C Read/Write 3-18
Capabilities Pointer 0x34 Read Only 3-22
Capability ID 0x40 Read Only 3-25
Class Code 0x09 Read Only 3-17
Command 0x04 Read/Write 3-13
Data 0x47 Read Only 3-28
Device ID 0x02 Read Only 3-13
Expansion ROM Base Address 0x30 Read/Write 3-21
Header Type 0x0E Read Only 3-19
Interrupt Line 0x3C Read/Write 3-23
Interrupt Pin 0x3D Read Only 3-23
Latency Timer 0x0D Read/Write 3-18
Max_Lat 0x3F Read Only 3-24
Min_Gnt 0x3E Read Only 3-24
Next Item Pointer 0x41 Read Only 3-25