Avago Technologies LSI8751D - Manual (Page 23)

LSI53C875 Benefits Summary 1-9
1.4.6 Reliability
The following features enhance the reliability of the LSI53C875:
•
2 kV ESD protection on SCSI signals.
•
Typical 300 mV SCSI bus hysteresis.
•
Protection against bus reflections due to impedance mismatches.
•
Controlled bus assertion times (reduces RFI, improves reliability, and
eases FCC certification).
•
Latch-up protection greater than 150 mA.
•
Voltage feed-through protection (minimum leakage current through
SCSI pads).
•
A high proportion (> 25%) of pins are power and ground.
•
Power and ground isolation of I/O pads and internal chip logic.
•
TolerANT technology which provides:
– Active negation of SCSI Data, Parity, Request, and Acknowledge
signals for improved fast SCSI transfer rates.
– Input signal filtering on SCSI receivers improves data integrity,
even in noisy cabling environments.
•
JTAG Boundary scan support (LSI53C875J, LSI53C875JB,
LSI53C875N only).
•
Extended PCI parity checking and generation (LSI53C875N only).
•
Extended SCSI parity checking.
1.4.7 Testability
The following features enhance the testability of the LSI53C875:
•
Access to all SCSI signals through programmed I/O.
•
SCSI loopback diagnostics.
•
SCSI bus signal continuity checking.
•
Support for single step mode operation.
•
Test mode (AND tree) to check pin continuity to the board (most
package options).
•
JTAG Boundary scan support (LSI53C875J, LSI53C875JB,
LSI53C875N only).