Avago Technologies LSI8751D - Manual (Page 38)

2-14 Functional Description
Master Data Parity Error DMA Status
(DSTAT)
, Bit 6
Set when the LSI53C875 as a master detects that a
target device has signaled a parity error during a data
phase.
Master Data Parity Error
Interrupt Enable DMA Interrupt
Enable (DIEN)
,
Bit 6
By clearing this bit, a Master Data Parity Error will not
cause IRQ/ to be asserted, but the status bit will be set
in the
DMA Status (DSTAT) register.
Extended Byte Parity
Error Interrupt Enable
(LSI53C875N only) DMA Interrupt
Enable (DIEN)
,
Bit 1
By clearing this bit, an Extended Byte Parity Error will
not cause IRQ/ to be asserted, but the status bit will be
set in the
DMA Status (DSTAT) register.
Table 2.3 SCSI Parity Control
EPC AESP Description
0 0 Does not check for parity errors. Parity is generated when sending
SCSI data. Asserts odd parity when sending SCSI data.
0 1 Does not check for parity errors. Parity is generated when sending
SCSI data. Asserts even parity when sending SCSI data.
1 0 Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts odd parity when sending SCSI
data.
1 1 Checks for odd parity on SCSI data received. Parity is generated
when sending SCSI data. Asserts even parity when sending SCSI
data.
1. Key:
EPC = Enable Parity Checking (bit 3, SCSI Control Zero (SCNTL0) ).
ASEP = Assert SCSI Even Parity (bit 2, SCSI Control One (SCNTL1) ).
2. This table only applies when the Enable Parity Checking bit is set.
Table 2.2 Bits Used for Parity Control and Generation (Cont.)
BIt Name Location Description