Avago Technologies LSI8751D - Manual (Page 260)

7-24 Instruction Set of the I/O Processor
7.4.2 Initiator Timing
Figure 7.17 through Figure 7.20 describe LSI53C875 Initiator timing.
Figure 7.15 Opcode Fetch, Nonburst
t
1
t
7
Addr
Out
BE
CLK
GPIO0_FETCH/
GPIO1_MASTER/
REQ/
GNT/
FRAME/
C_BE/
PAR/
(Driven by System)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by Arbiter)
(Driven by LSI53C875)
AD/
Target-Data)
(Driven by LSI53C875)
IRDY/
(Driven by Target)
(Driven by
LSI53C875-Addr;
Target-Data)
TRDY/
STOP/
DEVSEL/
(Driven by LSI53C875)
(Driven by Target)
(Driven by Target)
(Driven by
t
9
t
10
t
6
t
4
t
5
t
3
Data In
Addr
Out
Data In
CMD BE CMD
t
3
t
1
t
3
t
3
t
1
t
3
t
2
t
2
t
2
t
1
LSI53C875-Addr;
t
8