Avago Technologies LSI8751D - Manual (Page 305)

LSI53C875/875E PCI to Ultra SCSI I/O Processor IX-1
Index
Numerics
3.3/5 volt PCI interface 2-9
3-state 4-6
A
abort operation bit 5-31
aborted bit 5-24
,
5-50
active negation
see TolerANT technology
active termination 2-23
adder register 5-53
adder sum output register 5-53
always wide SCSI bit 5-74
arbitration
arbitration in progress bit 5-27
arbitration mode bits 5-3
immediate arbitration bit 5-8
in progress bit 5-27
lost arbitration bit 5-27
mode bits 5-3
priority encoder test bit 5-71
won arbitration bit 5-27
assert even SCSI parity bit 5-7
assert SATN/ on parity error bit 5-5
assert SCSI ACK/ signal bit 5-21
assert SCSI ATN/ signal bit 5-21
assert SCSI BSY/ signal bit 5-21
assert SCSI C_D/ signal bit 5-21
assert SCSI data bus bit 5-6
assert SCSI I_O signal bits 5-21
assert SCSI MSG/ signal bit 5-21
assert SCSI REQ/ signal bit 5-21
assert SCSI RST/ signal bit 5-7
assert SCSI SEL/ signal bit 5-21
B
bidirectional 4-6
big and little endian support 2-10
block move instructions 6-5
burst disable bit 5-40
burst length bits 5-43
,
5-47
burst opcode fetch enable bit 5-49
bus fault bit 5-24
,
5-50
byte
empty in DMA FIFO (FMT) 5-34
byte empty in DMA FIFO bit 5-35
byte full in DMA FIFO bit 5-35
byte offset counter bits 5-39
,
5-43
C
cache line size enable bit 5-51
cache mode, see PCI cache mode 3-4
chained block moves 2-34
to
2-38
SODL register 2-36
SWIDE register 2-36
wide SCSI receive bit 2-36
wide SCSI send bit 2-35
chained mode bit 5-9
chip revision level bits 5-37
chip test five register 5-42
chip test four register 5-40
chip test one register 5-35
chip test six register 5-43
chip test two register 5-35
chip test zero register 5-34
chip type bits 5-62
clear DMA FIFO bit 5-37
clear SCSI FIFO bit 5-76
clock address incrementor bit 5-42
clock byte counter bit 5-42
clock conversion factor bits 5-13
configuration registers. See PCI configuration registers
configured as I/O bit
5-36
configured as memory bit 5-36
connected bit 5-7
,
5-33
CTEST0 register 5-34
CTEST1 register 5-35
CTEST2 register 5-35
CTEST4 register 5-40
CTEST5 register 5-42
CTEST6 register 5-43
D
data acknowledge status bit 5-37
data path 2-16
data request status bit 5-37
data structure address register 5-31
data transfer direction bit 5-35
dataRD bit 5-62
dataWR bit 5-62
DBC register 5-44
DBLEN bit 3 5-72
DBLSEL bit 2 5-72
DCMD register 5-45
DCNTL register 5-51
destination I/O memory enable bit 5-48
DFIFO register 5-39
DIEN register 5-50