Avago Technologies LSI8751D - Manual (Page 230)

6-34 Instruction Set of the I/O Processor
The DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address
(DSA) registers are additional holding registers used during the Memory
Move. However, the contents of the Data Structure Address (DSA)
register are preserved.
IT[2:0] Instruction Type - Memory Move [31:39]
R Reserved [28:25]
These bits are reserved and must be zero. If any of these
bits are set, an illegal instruction interrupt occurs.
NF No Flush 24
When this bit is set, the LSI53C875 performs a Memory
Move without flushing the prefetch unit. When this bit is
clear, the Memory Move instruction automatically flushes
the prefetch unit. Use the No Flush option if the source
and destination are not within four instructions of the
current Memory Move instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Func-
tional Description.”
TC[23:0] Transfer Count [23:0]
The number of bytes to be transferred is stored in the
lower 24 bits of the first instruction word.
6.6.1 Read/Write System Memory from SCRIPTS
By using the Memory Move instruction, single or multiple register values
are transferred to or from system memory.
Because the LSI53C875 responds to addresses as defined in the Base
Address Zero (I/O) or Base Address One (Memory) registers, it can be
accessed during a Memory Move operation if the source or destination
address decodes to within the chip’s register space. If this occurs, the
register indicated by the lower seven bits of the address is taken as the
data source or destination. In this way, register values are saved to
system memory and later restored, and SCRIPTS can make decisions
based on data values in system memory.