Timers, 4 as the clock source – Lucent Technologies MN10285K User Manual
Page 122
Timers
16-Bit Timer Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
121
Panasonic
■
To set up timer 5:
Use the MOV instruction for this
setup and only use 16-bit write
operations.
This step stops the TM5BC
count and clears both TM5BC
and the S-R flip-flop to 0.
1.
Set the operating mode in the timer 5 mode register (TM5MD). Disable timer
5 counting and interrupts. Set the TM5UD[1:0] bits to b’10’, so that the count
direction is up when the TM5IA signal is high and down when the TM5IA sig-
nal is low. Select B
OSC
/4 as the clock source.
TM5MD (example)
x’00FE90’
2.
Write the intended looping value for timer 5 to TM5CA (valid settings:
x’0001’ to x’FFFF’). For TM5BC to count from x’0000’ to x’1FFF’, for
instance, write x’1FFF’ to TM5CA.
TM5CA (example)
x’00FE94’
3.
Write the timer 5 interrupt value (valid settings: x’0000’ to the value in
TM5CA) to TM5CB. Whenever the binary counter reaches the value in
TM5CB, in either up or down counting, a compare/capture B interrupt
occurs at the beginning of the next cycle.
TM5CB (example)
x’00FE98’
4.
Set the TM5NLD bit of the TM5MD register to 1 and the TM5EN bit to 0.
This enables TM5BC and the S-R flip-flop. This step ensures stable opera-
tion. If it is omitted, the binary counter may not count the first cycle. Do not
change any other operating modes during this step.
5.
Set TM5NLD and TM5EN to 1. This starts the timer. Counting begins at the
start of the next cycle.
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To enable timer 5 capture B interrupts:
Cancel all existing interrupt requests. Next, set the interrupt priority level in the
TM5CBLV[2:0] bits of the TM5CBICH register (levels 0 to 6), set the TM5BIE
bit to 1, and set the TM5BIR bit of TM5CBICL to 0. From this point on, an
interrupt request is generated whenever a timer 5 capture B event occurs.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TM5
EN
TM5
NLD
—
—
TM5
UD1
TM5
UD0
TM5
TGE
TM5
ONE
TM5
MD1
TM5
MD0
TM5
ECLR
TM5
LP
TM5
ASEL
TM5
S2
TM5
S1
TM5
S0
Setting:
0
0
0
0
1
0
0
0
0
0
0
1
1 or 0
0
1
1
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TM5
CA15
TM5
CA14
TM5
CA13
TM5
CA12
TM5
CA11
TM5
CA10
TM5
CA9
TM5
CA8
TM5
CA7
TM5
CA6
TM5
CA5
TM5
CA4
TM5
CA3
TM5
CA2
TM5
CA1
TM5
CA0
Setting:
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TM5
CB15
TM5
CB14
TM5
CB13
TM5
CB12
TM5
CB11
TM5
CB10
TM5
CB9
TM5
CB8
TM5
CB7
TM5
CB6
TM5
CB5
TM5
CB4
TM5
CB3
TM5
CB2
TM5
CB1
TM5
CB0
Setting:
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0