Interrupts, No interrupt requested 1: interrupt requested, Interrupt undetected 1: interrupt detected – Lucent Technologies MN10285K User Manual
Page 58: Disable 1: enable, Tm5udir: timer 5 underflow interrupt request flag, Tm5udid: timer 5 underflow interrupt detect flag
Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
57
Panasonic
TM5CAICL: Timer 5 Compare/Capture A Interrupt Control Register (Low) x’00FC6A’
TM5CAICL detects and requests timer 5 compare/capture interrupts. It is
an 8-bit access register. Use the MOVB instruction to access it.
TM5CAIR: Timer 5 compare/capture A interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM5CAID: Timer 5 compare/capture A interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM5CAICH: Timer 5 Compare/Capture A Interrupt Control Register (High) x’00FC6B’
TM5CAICH enables timer 5 compare/capture interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
The priority level for timer 5 compare/capture interrupts is written to the
TM5CBLV[2:0] field of the TM5CBICH register.
TM5CAIE: Timer 5 compare/capture A interrupt enable flag
0: Disable
1: Enable
TM5UDICL: Timer 5 Underflow Interrupt Control Register (Low)
x’00FC6C’
TM5UDICL detects and requests timer 5 underflow interrupts. It is an 8-
bit access register. Use the MOVB instruction to access it.
TM5UDIR: Timer 5 underflow interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM5UDID: Timer 5 underflow interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
Bit:
7
6
5
4
3
2
1
0
—
—
—
TM5CA
IR
—
—
—
TM5CA
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
TM5CA
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
TM5UD
IR
—
—
—
TM5UD
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R