Lucent Technologies MN10285K - Manual (Page 22)

General Description
MN102H Series Description
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
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Panasonic
■ Outstanding power savings
The MN102H series contains separate buses for instructions, data, and
peripheral functions, which distributes and reduces load capacitance, dra-
matically reducing overall power consumption. The series also supports
three HALT and STOP modes for even greater power savings.
The MN102H series is the flagship product for Panasonic’s new high-per-
formance architecture. Panasonic will expand the series as it strives to improve
the CPU core’s performance and speed, and as it develops devices incorporating
ASSPs, ASICs, internal EPROM, and other products to meet the needs of a wide
array of embedded designs.
1.3 MN102H Series Description
This section describes the basic architecture and functions of MN102H series
devices.
■ Processor status word (PSW)
The PSW contains the operation status flags and interrupt mask levels flags. Note
that the PSW for the MN102H series contains flags for both 16- and 24-bit
operation results .
ST: Saturation
This bit controls whether or not the CPU calculates a saturation limit for an
operation. When it is set to 1, the CPU executes a saturate operation, and
when it is 0, the CPU executes a normal operation. The PXST instruction
can reverse the meaning of this bit for the next (and only the next) instruc-
tion.
S[1:0]: Software control
These bits are the control field for OS software. It is reserved for the OS.
IE: Interrupt enable
If set, this flag enables maskable interrupts; if reset, it disables them.
IM[2:0]: Interrupt mask level
This field indicates the mask level (from 0 to 7) of interrupts that the CPU
will accept from its seven interrupt input pins. The CPU will not accept
any interrupt from a pin at a higher level than that indicated here.
VX: Extension overflow
If the operation causes the sign bit to change in a 24-bit signed number,
this flag is set; otherwise it is reset.
CX: Extension carry flag
If the operation resulted in a carry into (from addition) or a borrow out of
(from subtraction or a comparison) the most significant bit, this flag is set;
otherwise it is reset.
Flags for A ll 24 B its Flags for Low -O rder 16 Bits
B it: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— ST S1 S0 IE IM 2 IM 1 IM 0 V X C X N X ZX V F C F N F ZF
Reset: — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0