Interrupts, Disable 1: enable, No interrupt requested 1: interrupt requested – Lucent Technologies MN10285K User Manual
Page 67: Interrupt undetected 1: interrupt detected, Sets the priority from 0 to 6, Vbivir: vbivsync (1) interrupt request flag, Vbivid: vbivsync (1) interrupt detect flag, Vbivlv[2:0]: vbivsync (1) interrupt priority level, Vbivie: vbivsync (1) interrupt enable flag
Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
66
Panasonic
SCR0ICH: Serial 0 Reception End Interrupt Control Register (High)
x’00FC85’
SCR0ICH enables serial 0 reception end interrupts. It is an 8-bit access
register. Use the MOVB instruction to access it.
The priority level for serial 0 reception end interrupts is written to the
ANLV[2:0] field of the ANICH register.
SCR0IE: Serial 0 reception end interrupt enable flag
0: Disable
1: Enable
VBIVICL: VBIVSYNC (1) Interrupt Control Register (Low)
x’00FC88’
VBIVICL detects and requests VBIVSYNC (1) interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
VBIVIR: VBIVSYNC (1) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIVID: VBIVSYNC (1) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
VBIVICH: VBIVSYNC (1) Interrupt Control Register (High)
x’00FC89’
VBIVICH sets the priority level for and enables VBIVSYNC (1) inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
VBIVLV[2:0]: VBIVSYNC (1) interrupt priority level
Sets the priority from 0 to 6.
VBIVIE: VBIVSYNC (1) interrupt enable flag
0: Disable
1: Enable
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
SCR0
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
VBIVIR
—
—
—
VBIVID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
VBIV
LV2
VBIV
LV1
VBIV
LV0
—
—
—
VBIV
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R
R
R
R/W