Interrupts, Sets the priority from 0 to 6, Disable 1: enable – Lucent Technologies MN10285K User Manual
Page 63: No interrupt requested 1: interrupt requested, Interrupt undetected 1: interrupt detected, Adm3ie: address match 3 interrupt enable flag, Adm2ir: address match 2 interrupt request flag, Adm2id: address match 2 interrupt detect flag, Adm2ie: address match 2 interrupt enable flag
Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
62
Panasonic
ADM3ICH: Address 3 Match Interrupt Control Register (High)
x’00FC79’
ADM3ICH sets the priority level for and enables address match 3 inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
ADM3LV[2:0]: Address match 3 interrupt priority level
Sets the priority from 0 to 6.
ADM3IE: Address match 3 interrupt enable flag
0: Disable
1: Enable
ADM2ICL: Address 2 Match Interrupt Control Register (Low)
x’00FC7A’
ADM2ICL detects and requests address match 2 interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
ADM2IR: Address match 2 interrupt request flag
0: No interrupt requested
1: Interrupt requested
ADM2ID: Address match 2 interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
ADM2ICH: Address 2 Match Interrupt Control Register (High)
x’00FC7B’
ADM2ICH enables address match 2 interrupts. It is an 8-bit access regis-
ter. Use the MOVB instruction to access it.
The priority level for address match 2 interrupts is written to the
ADM3LV[2:0] field of the ADM3ICH register.
ADM2IE: Address match 2 interrupt enable flag
0: Disable
1: Enable
Bit:
7
6
5
4
3
2
1
0
—
ADM3
LV2
ADM3
LV1
ADM3
LV0
—
—
—
ADM3
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
ADM2
IR
—
—
—
ADM2
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
ADM2
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W