Interrupts, Disable 1: enable, No interrupt requested 1: interrupt requested – Lucent Technologies MN10285K User Manual
Page 59: Interrupt undetected 1: interrupt detected, Tm5udie: timer 5 underflow interrupt enable flag, Vbiwir: vbi (2) interrupt request flag, Vbiwid: vbi (2) interrupt detect flag, Vbiwie: vbi (2) interrupt enable flag
Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
58
Panasonic
TM5UDICH: Timer 5 Underflow Interrupt Control Register (High)
x’00FC6D’
TM5UDICH enables timer 5 underflow interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
The priority level for timer 5 underflow interrupts is written to the
TM5CBLV[2:0] field of the TM5CBICH register.
TM5UDIE: Timer 5 underflow interrupt enable flag
0: Disable
1: Enable
VBIWICL: VBI (2) Interrupt Control Register (Low)
x’00FC6E’
VBIWICL detects and requests VBI (2) interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
VBIWIR: VBI (2) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIWID: VBI (2) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
VBIWICH: VBI (2) Interrupt Control Register (High)
x’00FC6F’
VBIWICH register enables VBI (2) interrupts. It is an 8-bit access register.
Use the MOVB instruction to access it.
The priority level for VBI (2) interrupts is written to the TM5CBLV[2:0]
field of the TM5CBICH register.
VBIWIE: VBI (2) interrupt enable flag
0: Disable
1: Enable
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
TM5UD
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
VBIW
IR
—
—
—
VBIW
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
VBIW
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W