Ir remote signal receiver, Rmld is a 16-bit access register, Filter sampling cycle = f – Lucent Technologies MN10285K User Manual
Page 227: Clock = pwm3 01: filter sampling cycle = f, Clock = pwm1 10: filter sampling cycle = f, Clock = pwm3 11: filter sampling cycle = f, Clock = pwm1, Set to 1 when long data is detected, Set to 1 when short data is detected, Sp and spslw: switch clock frequencies
IR Remote Signal Receiver
IR Remote Signal Receiver Control Registers
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
226
Panasonic
RMLD: Remote Signal Leader Value Set Register
x’007EAC’
RMLD is a 16-bit access register.
fPWM1 = fSYSCLK/23,
fPWM3 = fSYSCLK/25,
fPWM5 = fSYSCLK/27,
fPWM6 = fSYSCLK/28, and
fPWM8 = fSYSCLK/210.
Do not set the leader value too
small. Leader detection and data
detection may occur
simultaneously.
SP and SPSLW: Switch clock frequencies
00: Filter sampling cycle = f
PWM6
, clock = PWM3
01: Filter sampling cycle = f
PWM3
, clock = PWM1
10: Filter sampling cycle = f
PWM8
, clock = PWM3
11: Filter sampling cycle = f
PWM5
, clock = PWM1
LD[3:0]: HEAMA data leader value
Set the four MSBs of the 6-bit leader value for HEAMA data in LD[3:0].
This 4-bit setting must be between 0 and 60 T
S
cycles. The default value is
x’6’. The two LSBs of the leader are always 0.
RMCS: Remote Signal Clock Status Register
x’007EA6’
RMCS indicates the result of the short/long data detection. It is a 16-bit
access register.
LONGDF: Long data format detection
Set to 1 when long data is detected.
SHORTDF: Short data format detection
Set to 1 when short data is detected.
TSCNT[5:0]: 6-bit counter value
RMSR: Remote Signal Reception Data Shift Register
x’007EA8’
RMTR: Remote Signal Reception Data Transfer Register
x’007EAA’
The microcontroller shifts received data into RMSR, converting it to paral-
lel data. After it shifts in 8 bits, it loads the data byte to RMTR. The CPU
reads the data from RMTR. The data shifts from LSB to MSB. RMSR and
RMTR are 8- or 16-bit access registers.
Bit:
7
6
5
4
3
2
1
0
SP
SPSLW
—
—
LD3
LD2
LD1
LD0
Reset:
0
0
0
0
0
1
1
0
R/W:
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
LONG
DF
SHORT
DF
TSCNT5 TSCNT4 TSCNT3 TSCNT2 TSCNT1 TSCNT0
Reset:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
RMSR7 RMSR6 RMSR5 RMSR4 RMSR3 RMSR2 RMSR1 RMSR0
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
RMTR7 RMTR6 RMTR5 RMTR4 RMTR3 RMTR2 RMTR1 RMTR0
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R