Lucent Technologies MN10285K - Manual (Page 242)

Closed-Caption Decoder
Closed-Caption Decoder Registers
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
241
Panasonic
CRI1E: CRI Capture Stop Timing Control Register 1 x’007E12’
(CRI1EW x’007E32’)
CRI1E[10:0]: Stop position for CRI capture 1
Valid range: x’000’ to x’7FF’
CRI2S: CRI Capture Start Timing Control Register 2 x’007E14
(CRI2SW x’007E34’)
CRI2S[10:0]: Start position for CRI capture 2
Valid range: x’000’ to x’7FF’
CRI2E: CRI Capture Stop Timing Control Register 2 x’007E16’
(CRI2EW x’007E36’)
CRI2E[10:0]: Stop position for CRI capture 2
Set this field so that the last CRI rising edge is included. The valid range is
x’000’ to x’7FF’.
DATAS: Data Capture Start Timing Control Register x’007E18’
(DATASW x’007E38’)
DATAS[10:0]: Start position for data capture
Set this field to the same start position as that for CRI detection (set in
CRI2S). The valid range is x’000’ to x’7FF’.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — —
CRI1E
10
CRI1E
9
CRI1E
8
CRI1E
7
CRI1E
6
CRI1E
5
CRI1E
4
CRI1E
3
CRI1E
2
CRI1E
1
CRI1E
0
Reset: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — —
CRI2S
10
CRI2S
9
CRI2S
8
CRI2S
7
CRI2S
6
CRI2S
5
CRI2S
4
CRI2S
3
CRI2S
2
CRI2S
1
CRI2S
0
Reset: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — —
CRI2E
10
CRI2E
9
CRI2E
8
CRI2E
7
CRI2E
6
CRI2E
5
CRI2E
4
CRI2E
3
CRI2E
2
CRI2E
1
CRI2E
0
Reset: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — —
DATA
S
10
DATA
S
9
DATA
S
8
DATA
S
7
DATA
S
6
DATA
S
5
DATA
S
4
DATA
S
3
DATA
S
2
DATA
S
1
DATA
S
0
Reset: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W