Lucent Technologies MN10285K - Manual (Page 46)

Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
45
Panasonic
XnICL (System Interrupt)
IR: Interrupt request flag
0: No interrupt requested
1: Interrupt requested
ID: Interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
The following is an example program setting an interrupt group’s priority level
(LV field) and enabling the interrupt group (IE) in the interrupt control register
(XnICH). Note that interrupts must be disabled during this routine.
Example 2-1 Setting the Interrupt Priority Level
... ;
and 0xf7ff,psw ;Clear the IE bit of the PSW.
nop ; Inserted to ensure that IE clears
nop ; completely, so XnICH is accessible.
mov d0,(XnICH) ;Write to LV/IE
mov (XnICH),d0 ;Synchronize with the store buffer.
or 0x0800,psw ;Set the IE bit of the PSW.
... ;
The program does not need to clear the IE bit of the PSW to disable interrupts
during interrupt servicing, since the interrupt service routine has already cleared
it.
You can replace the NOP instructions in the example above with any instruction
except for those that modify the PSW IE bit or the LV or IE bits of an XnICH
register. Inserting any of these instructions would cause interrupt error to occur.
The example includes two NOP instructions to ensure that the minimum number
of cycles required for a write to IE have passed. However, you can also insert
more than two NOPs.
Table 2-4 provides a list of the interrupt control registers, and a description of the
fields in each register follows.
Bit: 7 6 5 4 3 2 1 0
— — — IR — — — ID