Timers, Set the divide-by ratio for timer 4. to divide b, Set the timer 4 duty cycle. for a 2/5 b – Lucent Technologies MN10285K User Manual
Page 98
Timers
16-Bit Timer Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
97
Panasonic
P2DIR (example)
x’00FFE2’
■
To set up timer 4:
Use the MOV instruction for this
setup and only use 16-bit write
operations.
This step stops the TM4BC
count and clears both TM4BC
and the S-R flip-flop to 0.
1.
Set the operating mode in the timer 4 mode register (TM4MD). Disable
timer 4 counting and interrupts. Select up counting. Select B
OSC
/4 as the
clock source. Select the double-buffer operating mode.
TM4MD (example)
x’00FE80’
2.
Set the divide-by ratio for timer 4. To divide B
OSC
/4 by 5, write x’0004’ to
timer 4 compare/capture register A (TM4CA). (The valid range for TM4CA
is x’0001’ to x’FFFE’.)
TM4CA (example)
x’00FE84’
3.
Set the timer 4 duty cycle. For a 2/5 B
OSC
/4 duty cycle, write x’0001’ to
timer 4 compare/capture register B (TM4CB). (The valid range is -1
<
TM4CB
<
the TM4CA value.)
TM4CB (example)
x’00FE88’
4.
Write a dummy data word (of any value) to TM4CAX. In double-buffer
mode, TM4CA is compared to TM4CAX. The contents of TM4CA are
loaded to TM4CAX when TM4BC = TM4CAX. However, since TM4CAX
is undefined or x’0000’ before this operation starts, this initial dummy write
prevents timing errors.
5.
Write a dummy data word (of any value) to TM4CBX. In double-buffer
mode, TM4CB is compared to TM4CBX. The contents of TM4CB are
loaded to TM4CBX when TM4BC = TM4CBX. However, since TM4CBX
is undefined or x’0000’ before this operation starts, this initial dummy write
prevents timing errors.
Bit:
7
6
5
4
3
2
1
0
P2
DIR7
P2
DIR6
P2
DIR5
P2
DIR4
P2
DIR3
P2
DIR2
P2
DIR1
P2
DIR0
Setting:
0
1
0
0
0
0
0
0
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TM4
EN
TM4
NLD
—
—
TM4
UD1
TM4
UD0
TM4
TGE
TM4
ONE
TM4
MD1
TM4
MD0
TM4
ECLR
TM4
LP
TM4
ASEL
TM4
S2
TM4
S1
TM4
S0
Setting:
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TM4
CA15
TM4
CA14
TM4
CA13
TM4
CA12
TM4
CA11
TM4
CA10
TM4
CA9
TM4
CA8
TM4
CA7
TM4
CA6
TM4
CA5
TM4
CA4
TM4
CA3
TM4
CA2
TM4
CA1
TM4
CA0
Setting:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TM4
CB15
TM4
CB14
TM4
CB13
TM4
CB12
TM4
CB11
TM4
CB10
TM4
CB9
TM4
CB8
TM4
CB7
TM4
CB6
TM4
CB5
TM4
CB4
TM4
CB3
TM4
CB2
TM4
CB1
TM4
CB0
Setting:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1