Lucent Technologies MN10285K - Manual (Page 49)

Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
48
Panasonic
IAGR: Accepted Interrupt Group Number Register x’00FC0E’
IAGR returns the group number of an accepted interrupt, indicated in the
6-bit GN field. When the interrupt handler has to calculates the header
address for the interrupt service routine, it merely needs to add the contents
of IAGR to the header address for the table in which are registered the vec-
tor addresses for servicing all interrupts. IAGR is a 16-bit access register.
GN[5:0]: Group Number
Contains the group number multiplied by four.
EXTMD: External Interrupt Mode Register x’00FCF8’
EXTMD sets the trigger conditions for external interrupts. IQnTG[1:0]
sets the interrupt mode on the associated IRQ pin. Each IRQ pin can have
any polarity or edge setting. EXTMD is a 16-bit access register.
00: Active-low interrupt
01: Either-edge-triggered interrupt (positive or negative)
10: Negative-edge-triggered interrupt
11: Positive-edge-triggered interrupt
The watchdog timer interrupt is
provided for detecting and handling
racing. Normal operation is not
guaranteed if the program returns
after a watchdog interrupt. For
actions requiring returns, use a
timer interrupt.
WDICR: Watchdog Interrupt Control Register x’00FC42’
WDICR is an 8-bit access register.
WDID: Watchdog interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — — — — GN5 GN4 GN3 GN2 GN1 GN0 — —
Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — —
IQ5TG
1
IQ5TG
0
IQ4TG
1
IQ4TG
0
IQ3TG
1
IQ3TG
0
IQ2TG
1
IQ2TG
0
IQ1TG
1
IQ1TG
0
IQ0TG
1
IQ0TG
0
Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
— — — — — — — WDID
Reset: 0 0 0 0 0 0 0 0
R/W: R R R R R R R R/W