Lucent Technologies MN10285K - Manual (Page 298)

I
2
C Bus Controller
Functional Description
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
297
Panasonic
■ Register settings conversions to I
2
C protocol
The I
2
C bus controller converts the data in the I2CDTRM register to the I
2
C
protocol.
■ Transfer modes changes
A write to the I2CDTRM register indicates the transfer mode (master transmitter/
receiver or slave transmitter/receiver) for a new transfer. To minimize software
control, the hardware generates an interrupt each time a transfer ends. During
interrupt servicing, the SCL line stays low, then clears to high on a write to
I2CDTRM. (When the microcontroller is a slave transmitter and the transfer
ends, SCL goes high on a read to the I2CDREC register after an ACK = 1
(negative acknowledge) interrupt.)
■ Multimaster support
The hardware performs bus arbitration for a multimaster system. When it loses
an arbitration, the hardware immediately stops the data transfer and generates an
interrupt.
■ Address decoding
The I
2
C bus controller decodes the microcontroller’s address, set in the
I2CMYAD register, when the microcontroller is a slave device. It also decodes
the general code address (0).
■ Forced bus reset
Through software control, by a write to the I2CBRST register, the I
2
C bus con-
troller can force the SCL line to reset to low when a bus error occurs. This resets
the entire I
2
C bus controller circuit, leaving the microcontroller in slave receiver
mode. It does not change the contents of the I2CMYAD and I2CCLK registers.
■ Clock frequency adjustment
The I2CCLK register sets the serial clock frequency, allowing synchronization
with low-speed devices. With a 12-MHz oscillator, the maximum setting is 100
kHz and the minimum setting is 10 kHz.
■ Bus state monitoring
With the I2CBSTS register, the I
2
C bus controller determines the logic levels of
the SCL and SDA lines.