Interrupts, Sets the priority from 0 to 6, Disable 1: enable – Lucent Technologies MN10285K User Manual
Page 55: No interrupt requested 1: interrupt requested, Interrupt undetected 1: interrupt detected
Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
54
Panasonic
TM4CBICH: Timer 4 Compare/Capture B Interrupt Control Register (High)x’00FC61’
TM4CBICH sets the priority level for and enables timer 4 compare/capture
B interrupts. It is an 8-bit access register. Use the MOVB instruction to
access it.
TM4CBLV[2:0]: Timer 4 compare/capture B interrupt priority level
Sets the priority from 0 to 6.
TM4CBIE: Timer 4 compare/capture B interrupt enable flag
0: Disable
1: Enable
TM4CAICL: Timer 4 Compare/Capture A Interrupt Control Register (Low) x’00FC62’
TM4CAICL detects and requests timer 4 compare/capture interrupts. It is
an 8-bit access register. Use the MOVB instruction to access it.
TM4CAIR: Timer 4 compare/capture A interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM4CAID: Timer 4 compare/capture A interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM4CAICH: Timer 4 Compare/Capture A Interrupt Control Register (High)x’00FC63’
TM4CAICH enables timer 4 compare/capture interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
The priority level for timer 4 compare/capture interrupts is written to the
TM4CBLV[2:0] field of the TM4CBICH register.
TM4CAIE: Timer 4 compare/capture A interrupt enable flag
0: Disable
1: Enable
Bit:
7
6
5
4
3
2
1
0
—
TM4CB
LV2
TM4CB
LV1
TM4CB
LV0
—
—
—
TM4CB
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
TM4CA
IR
—
—
—
TM4CA
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
TM4CA
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W