Lucent Technologies MN10285K - Manual (Page 151)

Analog-to-Digital Converter
ADC Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
150
Panasonic
6.6 ADC Control Registers
The ADC contains thirteen registers—one control register (ANCTR) and twelve
data buffers (each associated with one of the ADIN pins). ANCTR controls the
operating conditions, and the read-only data buffers hold the results of the A/D
conversions.
AN0BUF–AN11BUF: ADIN0–ADIN11 Conversion Data Buffers x’00FF00’–x’00FF1C’
These buffers hold the 8-bit A/D conversion data. Their value is unknown
after reset.
Figure 6-11 Timing of Hardware-Controlled Intermittent Three-Channel A/D
Conversion
Table 6-2 ADC Control Registers
Register Address R/W Description
ANCTR x’00FF00’ R/W ADC control register
AN0BUF x’00FF08’ R ADIN0 conversion data buffer
AN1BUF x’00FF0A’ R ADIN1 conversion data buffer
AN2BUF x’00FF0C’ R ADIN2 conversion data buffer
AN3BUF x’00FF0E’ R ADIN3 conversion data buffer
AN4BUF x’00FF10’ R ADIN4 conversion data buffer
AN5BUF x’00FF12’ R ADIN5 conversion data buffer
AN6BUF x’00FF14’ R ADIN6 conversion data buffer
AN7BUF x’00FF16’ R ADIN7 conversion data buffer
AN8BUF x’00FF18’ R ADIN8 conversion data buffer
AN9BUF x’00FF1A’ R ADIN9 conversion data buffer
AN10BUF x’00FF1C’ R ADIN10 conversion data buffer
AN11BUF x’00FF1C’ R ADIN11 conversion data buffer
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — — — —
ANn
BUF7
ANn
BUF6
ANn
BUF5
ANn
BUF4
ANn
BUF3
ANn
BUF2
ANn
BUF1
ANn
BUF0
Reset: 0 0 0 0 0 0 0 0 — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Timer 1
underflow
Channel 0 Channel 1 Channel 2 Channel 0 Channel 1 Channel 2 Conversion
Interrupts