Lucent Technologies MN10285K - Manual (Page 77)

Low-Power Modes
CPU Control Register
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
76
Panasonic
3.3 CPU Control Register
CPUM: CPU Mode Control Register x’00FC00’
This register controls the invoking of all of the CPU modes.
NWDEN: Watchdog timer reset
0: Enable watchdog timer
1: Disable and clear watchdog timer
Setting the watchdog timer to 1, then setting it to 0 clears and restarts the
watchdog timer.
OSCID: Oscillator select
System clock monitor
0: Fast
1: Slow
STOP: STOP mode request
CPU operating state control. See table 3-2.
HALT: HALT mode request
CPU operating state control. See table 3-2.
OSC[1:0]: Oscillator control
See table 3-2.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NW
DEN
— — — — — — — — — —
OSC
ID
STOP HALT OSC1 OSC0
Reset: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R R R R R R R R R R R R/W R/W R/W R/W
Table 3-2 CPU Mode Bit Settings
STOP HALT OSC1 OSC0 CPU Mode
Clock
to CPU
System
Clock PLL CPU
0 0 0 0 NORMAL 24 MHz 12 MHz On On
0 0 1 1 SLOW 4 MHz 2 MHz Off On
0 1 0 0
HALT0 (Invoked
from NORMAL)
24 MHz 12 MHz On Off
0 1 1 1
HALT1 (Invoked
from SLOW)
4 MHz 2 MHz Off Off
1 0 x x STOP Off Off Off Off
Note: All unindicated bit settings are reserved.