6 8-bit timer control registers, Timers, Disable / 1: enable – Lucent Technologies MN10285K User Manual

Page 88: Do not load value / 1: load value, Tmnld: tmnbr value load to tmnbc, Tmns[1:0]: timer n clock source select

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Timers

8-Bit Timer Control Registers

MN102H75K/F75K/85K/F85K LSI User Manual

Panasonic Semiconductor Development Company

87

Panasonic

4.6

8-Bit Timer Control Registers

Table 4-2 shows the registers used to control the 8-bit timers. A binary counter

(TMnBC), a time base counter (TMnBR), and a timer mode register (TMnMD) is
associated with each 8-bit timer.

TM0BC–TM3BC: Timer n Binary Counter

x’00FE00’–x’00FE03’

TM0BR–TM3BR: Timer n Base Register

x’00FE10’–x’00FE13’

TM0MD–TM3MD: Timer n Mode Register

x’00FE20’–x’00FE23’

TMnEN: TMnBC count enable

0: Disable / 1: Enable

TMnLD: TMnBR value load to TMnBC

0: Do not load value / 1: Load value

TMnS[1:0]: Timer n clock source select

See table 4-1 on page 78 for clock sources. 00 = clock source 0, 01 = clock
source 1, 10 = clock source 2, and 11 = clock source 3.

Table 4-2 8-Bit Timer Control Registers

Register

Address

R/W

Description

Timer 0

TM0BC

x’00FE00’

R

Timer 0 binary counter

TM0BR

x’00FE10’

R/W

Timer 0 base register

TM0MD

x’00FE20’

R/W

Timer 0 mode register

Timer 1

TM1BC

x’00FE01’

R

Timer 1 binary counter

TM1BR

x’00FE11’

R/W

Timer 1 base register

TM1MD

x’00FE21’

R/W

Timer 1 mode register

Timer 2

TM2BC

x’00FE02’

R

Timer 2 binary counter

TM2BR

x’00FE12’

R/W

Timer 2 base register

TM2MD

x’00FE22’

R/W

Timer 2 mode register

Timer 3

TM3BC

x’00FE03’

R

Timer 3 binary counter

TM3BR

x’00FE13’

R/W

Timer 3 base register

TM3MD

x’00FE23’

R/W

Timer 3 mode register

Bit:

7

6

5

4

3

2

1

0

TMn

BC7

TMn

BC6

TMn

BC5

TMn

BC4

TMn

BC3

TMn

BC2

TMn

BC1

TMn

BC0

Reset:

0

0

0

0

0

0

0

0

R/W:

R

R

R

R

R

R

R

R

Bit:

7

6

5

4

3

2

1

0

TMn

BR7

TMn

BR6

TMn

BR5

TMn

BR4

TMn

BR3

TMn

BR2

TMn

BR1

TMn

BR0

Reset:

0

0

0

0

0

0

0

0

R/W:

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Bit:

7

6

5

4

3

2

1

0

TMn

EN

TMn

LD

TMn

S1

TMn

S0

Reset:

0

0

0

0

0

0

0

0

R/W:

R/W

R/W

R

R

R

R

R/W

R/W

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