Document Outline

• Read This First
• Contents
• Figures
• Tables
• Examples
• Cautions
• Introduction
  • TMS320 Family
    • History, Development, and Advantages of TMS320 DSPs
    • Typical Applications for the TMS320 Family
  • TMS320C2xx Generation
  • Key Features of the TMS320C2xx
• Architectural Overview
  • ’C2xx Bus Structure
  • Central Processing Unit
    • Central Arithmetic Logic Unit (CALU) and Accumulator
    • Scaling Shifters
    • Multiplier
    • Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers
  • Memory and I/O Spaces
    • Dual-Access On-Chip RAM
    • Single-Access On-Chip Program/Data RAM
    • Factory-Masked On-Chip ROM
    • Flash Memory
  • Program Control
  • On-Chip Peripherals
    • Clock Generator
    • CLKOUT1-Pin Control (CLK) Register
    • Hardware Timer
    • Software-Programmable Wait-State Generator
    • General-Purpose I/O Pins
    • Serial Ports
  • Scanning-Logic Circuitry
• Central Processing Unit
  • Input Scaling Section
  • Multiplication Section
    • Multiplier
    • Product-Scaling Shifter
  • Central Arithmetic Logic Section
    • Central Arithmetic Logic Unit (CALU)
    • Accumulator
    • Output Data-Scaling Shifter
  • Auxiliary Register Arithmetic Unit (ARAU)
    • ARAU and Auxiliary Register Functions
  • Status Registers ST0 and ST1
• Memory and I/O Spaces
  • Overview of the Memory and I/O Spaces
    • Pins for Interfacing to External Memory and I/O Spaces
  • Program Memory
    • Interfacing With External Program Memory
  • Local Data Memory
    • Data Page 0 Address Map
    • Interfacing With External Local Data Memory
  • Global Data Memory
    • Interfacing With External Global Data Memory
  • Boot Loader
    • Choosing an EPROM
    • Connecting the EPROM to the Processor
    • Programming the EPROM
    • Enabling the Boot Loader
    • Boot Loader Execution
    • Boot Loader Program
  • I/O Space
    • Accessing I/O Space
  • Direct Memory Access Using the HOLD Operation
    • HOLD During Reset
  • Device-Specific Information
    • TMS320C203 Address Maps and Memory Configuration
    • TMS320C204 Address Maps and Memory Configuration
• Program Control
  • Program-Address Generation
    • Program Counter (PC)
    • Stack
    • Micro Stack (MSTACK)
  • Pipeline Operation
  • Branches, Calls, and Returns
    • Unconditional Branches
    • Unconditional Calls
    • Unconditional Returns
  • Conditional Branches, Calls, and Returns
    • Using Multiple Conditions
    • Stabilization of Conditions
    • Conditional Branches
    • Conditional Calls
    • Conditional Returns
  • Repeating a Single Instruction
  • Interrupts
    • Interrupt Operation: Three Phases
    • Interrupt Table
    • Maskable Interrupts
    • Interrupt Flag Register (IFR)
    • Interrupt Mask Register (IMR)
    • Interrupt Control Register (ICR)
    • Nonmaskable Interrupts
    • Interrupt Service Routines (ISRs)
    • Interrupt Latency
  • Reset Operation
  • Power-Down Mode
    • Normal Termination of Power-Down Mode
    • Termination of Power-Down During a HOLD Operation
• Addressing Modes
  • Immediate Addressing Mode
    • Examples of Immediate Addressing
  • Direct Addressing Mode
    • Using Direct Addressing Mode
    • Examples of Direct Addressing
  • Indirect Addressing Mode
    • Current Auxiliary Register
    • Indirect Addressing Options
    • Next Auxiliary Register
    • Indirect Addressing Opcode Format
    • Examples of Indirect Addressing
    • Modifying Auxiliary Register Content
• Assembly Language Instructions
  • Instruction Set Summary
  • How To Use the Instruction Descriptions
    • Syntax
    • Operands
    • Opcode
    • Execution
    • Status Bits
    • Description
    • Words
    • Cycles
    • Examples
  • Instruction Descriptions
    • ABS
    • ABS
    • ADD
    • ADD
    • ADD
    • ADD
    • ADDC
    • ADDC
    • ADDS
    • ADDS
    • ADDT
    • ADDT
    • ADRK
    • AND
    • AND
    • AND
    • APAC
    • APAC
    • B
    • BACC
    • BANZ
    • BANZ
    • BCND
    • BCND
    • BIT
    • BIT
    • BITT
    • BITT
    • BLDD
    • BLDD
    • BLDD
    • BLDD
    • BLDD
    • BLPD
    • BLPD
    • BLPD
    • BLPD
    • CALA
    • CALL
    • CC
    • CC
    • CLRC
    • CLRC
    • CMPL
    • CMPR
    • DMOV
    • DMOV
    • IDLE
    • IN
    • IN
    • INTR
    • LACC
    • LACC
    • LACC
    • LACL
    • LACL
    • LACL
    • LACT
    • LACT
    • LAR
    • LAR
    • LAR
    • LDP
    • LDP
    • LPH
    • LPH
    • LST
    • LST
    • LST
    • LST
    • LT
    • LT
    • LTA
    • LTA
    • LTD
    • LTD
    • LTD
    • LTP
    • LTP
    • LTS
    • LTS
    • MAC
    • MAC
    • MAC
    • MAC
    • MACD
    • MACD
    • MACD
    • MACD
    • MACD
    • MAR
    • MAR
    • MPY
    • MPY
    • MPY
    • MPYA
    • MPYA
    • MPYS
    • MPYS
    • MPYU
    • MPYU
    • NEG
    • NEG
    • NMI
    • NOP
    • NORM
    • NORM
    • NORM
    • OR
    • OR
    • OR
    • OUT
    • OUT
    • PAC
    • POP
    • POP
    • POPD
    • POPD
    • PSHD
    • PSHD
    • PUSH
    • RET
    • RETC
    • ROL
    • ROR
    • RPT
    • RPT
    • SACH
    • SACH
    • SACL
    • SACL
    • SAR
    • SAR
    • SBRK
    • SETC
    • SETC
    • SFL
    • SFR
    • SFR
    • SPAC
    • SPH
    • SPH
    • SPL
    • SPL
    • SPLK
    • SPLK
    • SPM
    • SQRA
    • SQRA
    • SQRS
    • SQRS
    • SST
    • SST
    • SUB
    • SUB
    • SUB
    • SUB
    • SUBB
    • SUBB
    • SUBC
    • SUBC
    • SUBS
    • SUBS
    • SUBT
    • SUBT
    • TBLR
    • TBLR
    • TBLR
    • TBLW
    • TBLW
    • TBLW
    • TRAP
    • XOR
    • XOR
    • XOR
    • ZALR
    • ZALR
• On-Chip Peripherals
  • Control of On-Chip Peripherals
  • Clock Generator
    • Clock Generator Options
  • CLKOUT1-Pin Control (CLK) Register
  • Timer
    • Timer Operation
    • Timer Control Register (TCR)
    • Timer Counter Register (TIM) and Timer Period Register (PRD)
    • Setting the Timer Interrupt Rate
    • The Timer at Hardware Reset
  • Wait-State Generator
    • Generating Wait States With the READY Signal
    • Generating Wait States With the ’C2xx Wait-State Generator
  • General-Purpose I/O Pins
    • Input Pin BIO
    • Output Pin XF
    • Input/Output Pins IO0, IO1, IO2, and IO3
• Synchronous Serial Port
  • Overview of the Synchronous Serial Port
  • Components and Basic Operation
    • Signals
    • FIFO Buffers and Registers
    • Interrupts
    • Basic Operation
  • Controlling and Resetting the Port
    • Selecting a Mode of Operation (Bit 1 of the SSPCR)
    • Selecting Transmit Clock Source and Transmit Frame Sync Source (Bits 2 and 3 of the SSPCR)
    • Resetting the Synchronous Serial Port (Bits 4 and 5 of the SSPCR)
    • Using Transmit and Receive Interrupts (Bits 8–11 of the SSPCR)
  • Managing the Contents of the FIFO Buffers
  • Transmitter Operation
    • Burst Mode Transmission With Internal Frame Sync (FSM = 1, TXM = 1)
    • Burst Mode Transmission With External Frame Sync (FSM = 1, TXM = 0)
    • Continuous Mode Transmission With Internal Frame Sync (FSM = 0, TXM = 1)
    • Continuous Mode Transmission with External Frame Sync (FSM=0, TXM=0)
  • Receiver Operation
    • Burst Mode Reception
    • Continuous Mode Reception
  • Troubleshooting
    • Test Bits
    • Burst Mode Error Conditions
    • Continuous Mode Error Conditions
• Asynchronous Serial Port
  • Overview of the Asynchronous Serial Port
  • Components and Basic Operation
    • Signals
    • Baud-Rate Generator
    • Registers
    • Interrupts
    • Basic Operation
  • Controlling and Resetting the Port
    • Asynchronous Serial Port Control Register (ASPCR)
    • I/O Status Register (IOSR)
    • Baud-Rate Divisor Register (BRD)
    • Using Automatic Baud-Rate Detection
    • Using I/O Pins IO3, IO2, IO1, and IO0
    • Using Interrupts
  • Transmitter Operation
  • Receiver Operation
• TMS320C209
  • ’C209 Versus Other ’C2xx Devices
    • What Is the Same
    • What Is Different
    • Where to Find the Information You Need About the TMS320C209
  • ’C209 Memory and I/O Spaces
  • ’C209 Interrupts
    • ’C209 Interrupt Registers
    • IACK Pin
  • ’C209 On-Chip Peripherals
    • ’C209 Clock Generator Options
    • ’C209 Timer Control Register (TCR)
    • ’C209 Wait-State Generator
• Register Summary
  • A.1 Addresses and Reset Values
  • A.2 Register Descriptions
• TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
  • B.1 Using the Instruction Set Comparison Table
    • B.1.1 An Example of a Table Entry
    • B.1.2 Symbols and Acronyms Used in the Table
  • B.2 Enhanced Instructions
  • B.3 Instruction Set Comparison Table
• Program Examples
  • C.1 About These Program Examples
  • C.2 Shared Program Code
  • C.3 Task-Specific Program Code
  • C.4 Introduction to Generating Boot Loader Code
• Submitting ROM Codes to TI
• Design Considerations for Using XDS510 Emulator
  • E.1 Designing Your Target System’s Emulator Connector (14-Pin Header)
  • E.2 Bus Protocol
  • E.3 Emulator Cable Pod
  • E.4 Emulator Cable Pod Signal Timing
  • E.5 Emulation Timing Calculations
  • E.6 Connections Between the Emulator and the Target System
    • E.6.1 Buffering Signals
    • E.6.2 Using a Target-System Clock
    • E.6.3 Configuring Multiple Processors
  • E.7 Physical Dimensions for the 14-Pin Emulator Connector
  • E.8 Emulation Design Considerations
    • E.8.1 Using Scan Path Linkers
    • E.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL)
    • E.8.3 Using Emulation Pins
    • E.8.4 Performing Diagnostic Applications
• Glossary
• Index