ADTRAN 4200659L1 - Manual (Page 50)

Chapter 3. Configuration
3-4 MX2800 STS-1 User Manual 61200659L1-1
signal or reception of AIS will cause the unit to enter hold-over
mode. The STS-1 receive signal must be valid for at least 10
seconds for the unit to exit hold-over mode and restore loop timing.
When the unit is configured for F REE -R UN timing mode, timing is
derived from a +/-20 ppm internal reference providing a SONET
Minimum Clock (SMC).
Setting the unit to E XTERNAL timing mode configures the unit to
derive clocking from one of the two external sources selected in the
P RI E XT . C LOCK and S EC E XT . C LOCK options. These two entries
select which of the 28 active T1/E1 ports will be used as the
external clock source. The external clock source may be disabled (if
only one source exists, or no external clock sources are desired). A
valid clock source is one on which neither LOS or AIS conditions
exist. The selected T1/E1 may be a data carrying tributary. When
both sources are configured, failure of one source will cause the
unit to switch to the other source (if it is a valid source). Failure of
both sources will cause the unit to enter hold-over mode. At least
one external clock source must be valid for at least 10 seconds for
the unit to exit hold-over mode and restore external clock timing.
XCV Threshold
The XCV T HRESHOLD (excessive code violations threshold) sets a
limit on code violations accepted by the unit before it switches
controller cards. If set to
D ISABLED , code violations will not cause
the unit to switch controller cards. The threshold limits are
described in the following chart:
Switching between P RI mary and S EC ondary external clock sources
is non-reverting.