AMD SB600 User Manual
Page 110
©2008 Advanced Micro Devices, Inc.
SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual
Proprietary
Page 110
TestMode- RW - 16 bits - [PCI_Reg: 6C]
Field Name
Bits
Default
Description
DMA_Timing
0
0b
To be used by BIOS only; when set, legacy DMA will insert 1
extra idle clock in between requests. Software should always
set this bit.
TestMode
4:1
0h
These bits are for testing only. Software should not write to
these bits.
PCIB_SReset_En Mask
5
0b
When set, PCIB_SReset_En (x3e bit 22 of PCI Bridge) will be
writable.
TestMode
15:6
000h
These bits are for testing only. Software should not write to
these bits.
TestMode register
IoApic_Conf- RW - 32 bits - [PCI_Reg: 74h]
Field Name
Bits
Default
Description
Reserved 2:0
000b
Mem_IO_Map 3
1b
Base
address
mapping
1 = memory map
0 = IO map
Reserved 4
0b
IoApic_Addr 31:5
1111_
1110_
1100_
0000_
0000_
0000_
000b
Base address for IOAPIC
IoApic_Conf register.
IoAddrEnable - RW - 32 bits - [PCI_Reg: 78h]
Field Name
Bits
Default
Description
DmaAddr_En 0
1b
0x000:0x01F,
0x080:0x08F, 0x0C0:0xCF, 0x0D0:0x0DF,
0x40B, 0x4D6,
PitAddr_En
1
1b
0x40,0x41, 0x42, 0x43
NmiAddr_En 2
1b
0x70
RtcAddr_En 3
1b
0x71
Misc_Enable1 4
1b
0xC14
Misc_Enable2 5
1b
0xC49,
0xC4A
Misc_Enable3 6
1b
0xC52
Misc_Enable4 7
1b
0xC6C
Misc_Enable5 8
1b
0xC6F
PM_Addr_Enable 9
1b
0xCD6,0
xCD7
Reserved 10
0b
Cms_Enable
11
1b
Address 0xC50, 0xC51
Reserved 13:12
00b
Port92Enable
14
1b
Port 92 enable
Reserved 31:15
00000h
IoAddrEnable Register: When a bit is set, this block will decode the corresponding address. If the bit is cleared, this
block will not claim the corresponding address. This is to allow the legacy port to be behind the PCI bridge.
GPIO_69_68_66_65_Cntrl - RW – 16 bits - [PCI_Reg: 7Eh]
Field Name
Bits
Default
Description
GPIO_Out
3:0
0h
Write 1 to set and 0 to clear each of the GPIO port providing
the corresponding bits [7:4] are enabled
Bit[0] for GPIO65/BMREQ#
Bit[1] for GPIO66/LLB#
Bit[2] for GPIO68/LDRQ1#
Bit[3] for GPIO69/RTC_IRQ#