AMD SB600 User Manual
Page 243
©2008 Advanced Micro Devices, Inc.
HD Audio Controllers Registers
AMD SB600 Register Reference Manual
Proprietary
Page 243
DMA Position Lower Base Address – RW – 32 bits – [Mem_Reg: Base + 70h]
Field Name
Bits
Default
Description
DMA Position Lower Base
Address
31:7
0000000h Contains the upper 25 bits of the lower 32 bits of the DMA
Position Buffer Base Address.
This same address is used by the Flush Control, and must
be programmed with a valid value before the Flush Control
is initiated.
DMA Position Upper Base Address – RW – 32 bits – [Mem_Reg: Base + 74h]
Field Name
Bits
Default
Description
DMA Position Upper Base
Address
31:0 00000000
h
Upper 32 bits of the DMA Position Buffer Base Address.
This same address is used by the Flush Control, and must
be programmed with a valid value before the Flush Control
is initiated.
Stream Descriptor Control – RW – 24 bits
Input Stream 0 - [Mem_Reg: Base + 80h]
Input Stream 1 - [Mem_Reg: Base + A0h]
Input Stream 2 - [Mem_Reg: Base + C0h]
Input Stream 3 - [Mem_Reg: Base + E0h]
Output Stream 0 - [Mem_Reg: Base + 100h]
Output Stream 1 - [Mem_Reg: Base + 120h]
Output Stream 2 - [Mem_Reg: Base + 140h]
Output Stream 3 - [Mem_Reg: Base + 160h]
Field Name
Bits
Default
Description
Stream Reset
0
0b
Writing a “1” causes the corresponding stream to be reset.
The Stream Descriptor registers (except this bit), FIFO’s
and cadence generator for the corresponding stream are
reset. After the stream hardware has completed
sequencing into the reset state, it will report a “1” in this bit.
Software must read a “1’ from this bit to verify that the
stream is in reset.
Writing a “0” causes the corresponding stream to exit reset.
When the stream hardware is ready to begin operation, it
will report a “0” in this bit. Software must read a “0” from
this bit before accessing any of the stream registers. The
Run bit must be cleared before asserting SRST (Stream
Reset).
Stream Run
1
0b
When set to “1”, the DMA engine associated with this input
stream will be enabled to transfer data in the FIFO to main
memory. When cleared to “0”, the DMA engine associated
with this input stream will be disabled. If the corresponding
SSYNC bit is “0”, input stream data will be taken from the
link and moved to the FIFO and an over-run may occur.
Interrupt On Completion
Enable
2
0b
Controls whether an interrupt is generated when the Buffer
Completion Interrupt Status is set
FIFO Error Interrupt
Enable
3
0b
Controls whether an interrupt is generated when the FIFO
Error is set.
Descriptor Error Interrupt
Enable
4
0b
Controls whether an interrupt is generated when the
Descriptor Error Status is set.
Reserved
15:5
000h
Reserved. Software must do a read-modify-write to
preserve the value of these bits.