AMD SB600 - Manual (Page 83)

©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual Proprietary Page 83
USBCMD – RW - 32 bits - [EOR_Reg : EHCI_EOR + 00h]
Field Name Bits Default Description
Host Controller
Reset
(HCRESET)
1 0b This control bit is used by software to reset the host controller. The
effects of this on Root Hub registers are similar to a Chip Hardware
Reset. When software writes a one to this bit, the Host Controller resets
its internal pipelines, timers, counters, state machines, etc. to their initial
value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. PCI
Configuration registers are not affected by this reset. All operational
registers, including port registers and port state machines are set to their
initial values. Port ownership reverts to the companion host controller(s).
Software must reinitialize the host controller in order to return the host
controller to an operational state. This bit is set to zero by the Host
Controller when the reset process is complete. Software cannot
terminate the reset process early by writing a zero to this register.
Software should not set this bit to a one when the HCHalted bit in the
USBSTS register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.
Frame List Size 3:2 00b This field is R/W only if Programmable Frame List Flag in the
HCCPARAMS registers is set to a one. This field specifies the size of
the frame list. The size the frame list controls which bits in the Frame
Index Register should be used for the Frame List Current index. Values
mean:
00b = 1024 elements (4096 bytes) Default value
01b = 512 elements (2048 bytes)
10b = 256 elements (1024 bytes) – for resource-constrained
environments
11b = Reserved
[Read/Write or Read-only]
Periodic
Schedule
Enable 4 0b This bit controls whether the host controller skips processing the Periodic
Schedule.
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the Periodic
Schedule.
Asynchronous
Schedule
Enable 5 0b This bit controls whether the host controller skips processing the
Asynchronous Schedule.
0b = Do not process the Asynchronous Schedule
1b = Use the ASYNCLISTADDR register to access the Asynchronous
Schedule.
Interrupt on
Async Advance
Doorbell 6 0b This bit is used as a doorbell by software to tell the host controller to
issue an interrupt the next time it advances asynchronous schedule.
Software must write a 1 to this bit to ring the doorbell. When the host
controller has evicted all appropriate cached schedule state, it sets the
Interrupt on Async Advance
status bit in the USBSTS register. If the
Interrupt on Async Advance Enable bit in the USBINTR register is a one
then the host controller will assert an interrupt at the next interrupt
threshold. The host controller sets this bit to a zero after it has set the
Interrupt on Async Advance
status bit in the USBSTS register to a one.
Software should not write a one to this bit when the asynchronous
schedule is disabled. Doing so will yield undefined results.
Light Host
Controller Reset
(Optional) 7 0b This control bit is not required. If implemented, it allows the driver to
reset the EHCI controller without affecting the state of the ports or the
relationship to the companion host controllers. For example, the
PORSTC registers should not be reset to their default values and the CF
bit setting should not go to zero (retaining port ownership relationships).
A host software read of this bit as zero indicates the Light Host Controller
Reset has completed and it is safe for host software to re-initialize the
host controller. A host software read of this bit as a one indicates the
Light Host Controller Reset has not yet completed.
If not implemented a read of this field will always return a zero.