AMD SB600 User Manual

Page 54

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©2008 Advanced Micro Devices, Inc.

OCHI USB 1.1 and EHCI USB 2.0 Controllers

AMD SB600 Register Reference Manual

Proprietary

Page 54

HcControl - 32 bits - [MEM_Reg : 04h]

Field Name

Bits

Default

HCD

HC

Description

IR 8

0b

RW

R

InterruptRouting
This bit determines the routing of interrupts generated
by events registered in HcInterruptStatus. If clear, all
interrupts are routed to the normal host bus interrupt
mechanism. If set, interrupts are routed to the System
Management Interrupt. HCD clears this bit upon a
hardware reset, but it does not alter this bit upon a
software reset. HCD uses this bit as a tag to indicate
the ownership of HC.

RWC 9

0b

RW

RW

RemoteWakeupConnected
This bit indicates whether HC supports remote
wakeup signaling. If remote wakeup is supported and
used by the system it is the responsibility of system
firmware to set this bit during POST. HC clears the bit
upon a hardware reset but does not alter it upon a
software reset. Remote wakeup signaling of the host
system is host-bus-specific and is not described in
this specification.

RWE 10

0b

RW

R

RemoteWakeupEnable
This bit is used by HCD to enable or disable the
remote wakeup feature upon the detection of
upstream resume signaling. When this bit is set and
the ResumeDetected bit in HcInterruptStatus is set, a
remote wakeup is signaled to the host system.
Setting this bit has no impact on the generation of
hardware interrupt.

Reserved 31:11

Reserved

HcCommandStatus - 32 bits - [MEM_Reg : 08h]

Field Name

Bits

Default

HCD

HC

Description

HCR 0

0b

RW

RW

HostControllerReset
This bit is set by HCD to initiate a software reset of
HC.Regardless of the functional state of HC, it moves
to the

US

B

SUSPEND

state in which most of the

operational registers are reset except those stated
otherwise; e.g., the InterruptRouting field of
HcContro

l, and no Host bus accesses are allowed.

This bit is cleared by HC upon the completion of the
reset operation. The reset operation must be
completed within 10 ms. This bit, when set, should
not cause a reset to the Root Hub and no subsequent
reset signaling should be asserted to its downstream
ports.

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