AMD SB600 - Manual (Page 282)

©2008 Advanced Micro Devices, Inc. GPIO/GPOC
AMD SB600 Register Reference Manual Proprietary Page 282
Pin Name
(Note 1) Multi-function
Selection Output Enable
(On SMBus
Controller)
Bus 00h/ Dev14h/
Fun00
Input if GPI
(On SMBus
Controller)
Bus 00h/
Dev14h/ Fun00 Output if GPO
(On SMBus
Controller)
Bus 00h/
Dev14h/ Fun00 Power
Domain
Notes:
1– In this table, the “GPIO” portion of the pin name has been put at the front of the names for the sake of clarity, making the pin names
different from how they appear in the AMD SB600 Databook.
2– Register A9h[7:0] is addressed as A8[15:8] in some AMD documents.
3– Register AAh[7:0] is addressed as A8[23:16] in some AMD documents.
4– Register BDh[7:0] is addressed as BCh[15:8] in some AMD documents.
5– Register 0A2h[15:0] is addressed as 0A0h[31:16] in some AMD documents.
4.1.2 GPOC
The two pairs of GPOC[3:2] and GPOC[1:0] pins are multi-purpose pins. They can be used as SMBus data
and clock pins or general purpose input/output pins. When used as output pins, they are open collectors and
need pull-up resistors for output high. Input/output programming is accomplished through the register pair
C50h/C51h in index/data mode.
GPOC[3:2] pins are in the S5 power plane. GPOC[1:0] pins are in the S0 power plane.
The index register 12h is used to access GPOC pins and is defined as follows:
Table 4-2: GPOC Pins
IO C50h/C51h
index 12h
Bit
Field Name Default Description
0 GPOC0 Status -- GPOC0 Input read status
1 GPOC1 Status -- GPOC1 Input read status
2 GPOC0_OE 1 0 = GPOC0 is asserted low
1 = GPOC0 is tri-state
3 GPOC1_OE 1 0 = GPOC1 is asserted low
1 = GPOC1 is tri-state
4 GPOC2 Status -- GPOC2 Input read status
5 GPOC3 Status -- GPOC3 Input read status
6 GPOC2_OE 1 0: GPOC2 is asserted low
1: GPOC2 is tri-state
7 GPOC3_OE 1 0: GPOC3 is asserted low
1: GPOC3 is tri-state