AMD SB600 - Manual (Page 246)

©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers
AMD SB600 Register Reference Manual Proprietary Page 246
Stream Descriptor Cyclic Buffer Length – RW – 32 bits
Input Stream 0 - [Mem_Reg: Base + 88h]
Input Stream 1 - [Mem_Reg: Base + A8h]
Input Stream 2 - [Mem_Reg: Base + C8h]
Input Stream 3 - [Mem_Reg: Base + E8h]
Output Stream 0 - [Mem_Reg: Base + 108h]
Output Stream 1 - [Mem_Reg: Base + 128h]
Output Stream 2 - [Mem_Reg: Base + 148h]
Output Stream 3 - [Mem_Reg: Base + 168h]
Field Name Bits Default Description
Cyclic Buffer Length 31:0 00000000
h
Indicates the number of bytes in the complete cyclic buffer.
Link Position in Buffer will be reset when it reaches this
value.
Software may only write to this register after Global Reset,
Controller Reset, or Stream Reset has occurred. Once the
Run bit has been set to enable the engine, software must
not write to this register until after the next reset is
asserted, or undefined events will occur.
Stream Descriptor Last Valid Index – RW – 16 bits
Input Stream 0 - [Mem_Reg: Base + 8Ch]
Input Stream 1 - [Mem_Reg: Base + ACh]
Input Stream 2 - [Mem_Reg: Base + CCh]
Input Stream 3 - [Mem_Reg: Base + ECh]
Output Stream 0 - [Mem_Reg: Base + 10Ch]
Output Stream 1 - [Mem_Reg: Base + 12Ch]
Output Stream 2 - [Mem_Reg: Base + 14Ch]
Output Stream 3 - [Mem_Reg: Base + 16Ch]
Field Name Bits Default Description
Last Valid Index 7:0 00h The value written to this register indicates the index for the
last valid Buffer Descriptor in BDL. After the controller has
processed this descriptor, it will wrap back to the first
descriptor in the list and continue processing.
LVI (Last Valid Index) must be “1”; i.e., there must be at
least two valid entries in the BDL before DMA operations
can begin.
This value should not be modified except when the Run bit
is “0”.
Reserved 15:8 00h Reserved. Software must do a read-modify-write to
preserve the value of these bits.