AMD SB600 - Manual (Page 150)

©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 150
AcpiSmiCmdLo - RW – 8 bits - [PM_Reg: 2Ah]
Field Name Bits Default Description
AcpiSmiCmdLo 7:0 00h These bits define the least significant byte of the 16 bit I/O
base address of the ACPI SMI Command block. Bit 0
corresponds to Addr[0] and bit 7 corresponds to Addr[7]. The
address is required to be DWORD-aligned (Bit[1:0]=00b)
AcpiSmiCmdLo register.
AcpiSmiCmdHi - RW – 8 bits - [PM_Reg: 2Bh]
Field Name Bits Default Description
AcpiSmiCmdHi 7:0 00h These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiSmiCmdHi register.
AcpiPmaCntBlkLo - RW – 8 bits - [PM_Reg: 2Ch]
Field Name Bits Default Description
AcpiPmaCntBlkLo 7:0 00h These bits define the least significant byte of the 16 bit I/O
base address of the ACPI power management additional
control block. Bit 0 corresponds to Addr[0] and bit 7
corresponds to Addr[7].
AcpiPmaCntBlkLo register.
AcpiPmaCntBlkHi - RW – 8 bits - [PM_Reg: 2Dh]
Field Name Bits Default Description
AcpiPmaCntBlkHi 7:0 00h These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiPmaCntBlkHi register.
GEvtConfig0 – RW – 8 bits - [PM_Reg: 30h]
Field Name Bits Default Description
GEvtConfig0 7:0 00h GEVENT Configuration. These 8 bits are used for
configuring general purpose events 0-3. Two bits for each
event pin. Bit[1:0] for GEVENT[0], bit[3:2] for GEVENT[1]
and so on
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GEVENT to generate SMI#
10 GEVENT to generate SMI# followed by SCI
11 GEVENT to generate IRQ13
GEvtConfig0 register.
GEvtConfig1 – RW – 8 bits - [PM_Reg: 31h]
Field Name Bits Default Description
GEvtConfig1 7:0 00h GEVENT Configuration. These 8 bits are used for
configuring General Purpose Events 4-7. Two bits for each
event pin. Bit[1:0] for GEVENT[4], bit[3:2] for GEVENT[5]
and so on
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GEVENT to generate SMI#
10 GEVENT to generate SMI# followed by SCI
11 GEVENT to generate IRQ13
GEvtConfig1 register.