AMD SB600 User Manual

Page 211

Advertising
background image


©2008 Advanced Micro Devices, Inc.

AC ’97 Controller Functional Descriptions

AMD SB600 Register Reference Manual

Proprietary

Page 211

Output DMA Fifo info- R - 32 bits - [MEM_Reg: 8Ch]

Field Name

Bits

Default

Description

Out FIFO Used

6:0

00h

Number of filled FIFO entries of output DMA.

Reserved 7

0b

Out FIFO Free

14:8

5Ah

Number of free FIFO entries of output DMA. Default is 90 (size of
output fifo)

Reserved 31:15

00000h

SPDIF Status bits reg1- RW - 32 bits - [MEM_Reg: 90h]

Field Name

Bits

Default

Description

SPDIF Status bits

31:0

0000_0

000h

The bits in this reg are used on spdif bus as status bits. Each spdif
bus frame has a status bit. Spdif bus frame counts from 0~191
repeatedly, so there are 192 status bits. Software can write to this
register (and the following few registers) to decide what status bits
value to output on spdif bus.
Bits 0~31 in this register correspond to frame 0~31 on spdif bus.

SPDIF Status bits reg2- RW - 32 bits - [MEM_Reg: 94h]

Field Name

Bits

Default

Description

SPDIF Status bits

31:0

0000_0

000h

Same definition as reg0x90.
Bits 0~31 in this register correspond to frame 32~63 on spdif bus.

SPDIF Status bits reg3- RW - 32 bits - [MEM_Reg: 98h]

Field Name

Bits

Default

Description

SPDIF Status bits

31:0

0000_0

000h

Same definition as reg0x90.
Bits 0~31 in this register correspond to frame 64~95 on spdif bus.

SPDIF Status bits reg4- RW - 32 bits - [MEM_Reg: 9Ch]

Field Name

Bits

Default

Description

SPDIF Status bits

31:0

0000_0

000h

Same definition as reg0x90.
Bits 0~31 in this register correspond to frame 96~127 on spdif bus.

SPDIF Status bits reg5- RW - 32 bits - [MEM_Reg: A0h]

Field Name

Bits

Default

Description

SPDIF Status bits

31:0

0000_0

000h

Same definition as reg0x90.
Bits 0~31 in this register correspond to frame 128~159 on spdif bus.

SPDIF Status bits reg6- RW - 32 bits - [MEM_Reg: A4h]

Field Name

Bits

Default

Description

SPDIF Status bits

31:0

0000_0

000h

Same definition as reg0x90.
Bits 0~31 in this register correspond to frame 160~191 on spdif bus.

Advertising