AMD SB600 - Manual (Page 134)

©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 134
Dma_Ch7Cnt - RW – 8 bits - [IO_Reg: CEh]
Field Name Bits Default Description
Dma2_Ch7Cnt 7:0 00h Channel 7 DMA base and current count
Dma2_Ch7Cnt register
Dma_Status - RW – 8 bits - [IO_Reg: D0h]
Field Name Bits Default Description
Dma_Status 7:0 00h DMA2 status register
Dma_Status register
Dma_WriteRequest - RW – 8 bits - [IO_Reg: D2h]
Field Name Bits Default Description
Dma_WriteRequest 7:0 00h DMA2 request register
Dma_WriteRequest register
Dma_WriteMask - RW – 8 bits - [IO_Reg: D4h]
Field Name Bits Default Description
Dma_WriteMask 7:0 00h DMA2 channel mask register
Dma_WriteMask register
Dma_WriteMode - RW – 8 bits - [IO_Reg: D6h]
Field Name Bits Default Description
Dma_WriteMode 7:0 00h DMA2 mode register
Dma_WriteMode register
Dma_Clear - RW – 8 bits - [IO_Reg: D8h]
Field Name Bits Default Description
Dma_Clear 7:0 00h Channel 4-7 clear byte pointer
Dma_Clear register
Dma_Clear - RW – 8 bits - [IO_Reg: DAh]
Field Name Bits Default Description
Dma_Clear 7:0 00h Channel 4-7 DMA master clear
Dma_Clear register
Dma_ClrMask - RW – 8 bits - [IO_Reg: DCh]
Field Name Bits Default Description
Dma_ClrMask 7:0 00h Channel 4-7 DMA Clear Mask
Dma_ClrMask register
Dma_ClrMask - RW – 8 bits - [IO_Reg: DEh]
Field Name Bits Default Description
Dma_AllMask 7:0 00h DMA2 mask register
Dma_AllMask register
NCP_Error - RW – 8 bits - [IO_Reg: F0h]
Field Name Bits Default Description
Reserved 6:0 00h
WarmBoot 7 0b Warm or cold boot indicator
0 – Cold
1 – Warm, this bit is set when any value is written to this
register;