AMD SB600 User Manual
Page 285
©2008 Advanced Micro Devices, Inc.
GEVENT/GPE/GPM/ExtEvent
AMD SB600 Register Reference Manual
Proprietary
Page 285
Pin Name
(*Note 1)
Multi-Function
Selection
Configure Bit
00 – SCI or SMI#
01 – SMI#
10 – SMI#
followed by SCI
11 - IRQ13
Trigger Configure
0–Falling edge
1–Rising edge
Enable
ACPI Event
Status
(Write 1 to ACPI
GPE00h Bit to
Clear)
Power
Domain
GPM3/
USB_OC3#
SMBus
Reg64h[Bit 23]
=1 to Enable
GPE
PM IO
Reg33h[Bit5:4]
PM IO
Reg37h[Bit 6]
ACPI
GPE04h[Bit22]
PM IO
Reg3Ah[Bit 6]
or ACPI
GPE00 [Bit 22]
S5
GPM4/
USB_OC4#
SMBus
Reg64h[Bit 19]
=1 to enable
GPE
PM IO
Reg34h[Bit3:2]
PM IO
Reg38h[Bit 1]
ACPI
GPE04h[Bit25]
PM IO
Reg3Bh[Bit 1]
or ACPI
GPE00h[Bit25]
S5
GPM5/
USB_OC5#
SMBus
Reg64h[Bit 19]
=1 to enable
GPE
PM IO
Reg34h[Bit5:4]
PM IO
Reg38h[Bit 2]
ACPI
GPE04h[Bit26]
PM IO
Reg3Bh[Bit 2]
or ACPI
GPE00h[Bit26]
S5
GPM6/
BLINK
PM IO
Reg7Ch[Bit 3:2]
00: GPM6
01/10/11: BLINK
1/4Hz, 1/2Hz,
and always-on
SMBus
Reg64h[Bit 18]
=1 to enable
GPE
PM IO
Reg35h[Bit1:0]
PM IO
Reg38h[Bit 4]
ACPI
GPE04h[Bit28]
PM IO
Reg3Bh[Bit 4]
or ACPI
GPE00h[Bit28]
S5
GPM7/
SYS_
RESET#
PM IO
Reg55h[Bit 2]
0: GPM7
1: SYS_RESET#
SMBus
Reg64h[Bit 17]
=1 to enable
GPE
PM IO
Reg35h[Bit3:2]
PM IO
Reg38h[Bit 5]
ACPI
GPE04h[Bit29]
PM IO
Reg3Bh[Bit 5]
or ACPI
GPE00h[Bit29]
S5
GPM8/
USB_OC8#/
AZ_DOCK_
RST#
PM IO
Reg8Dh[Bit 2]
0: GPM8
1:
AZ_DOCK_RST
#
SMBus
Reg64h[Bit 23]
=1 to enable
GPE
PM IO
Reg33h[Bit7:6]
PM IO
Reg37h[Bit 7]
ACPI
GPE04h[Bit23]
PM IO
Reg3Ah[Bit 7]
or ACPI
GPE00 [Bit 23]
S5
GPM9/
USB_OC9#/
SLP_S2
PM IO
Reg8Dh[Bit 1]
0: GPM9
1: SLP_S2
PM IO
Reg3Dh[Bit3:2]
Always falling edge ACPI
GPE04h[Bit14]
ACPI
GPE00 [Bit 14]
S5
EXTEVENT
0#/
RI#
SMBus
Reg64h[Bit 22]
=1 to enable
GPE
PM IO
Reg32h[Bit1:0]
PM IO
Reg37h[Bit 0]
ACPI
GPE04h[Bit16]
PM IO
Reg3Ah[Bit 0]
or ACPI
GPE00h[Bit16]
S5