AMD SB600 - Manual (Page 148)

©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 148
IOMonitorStatus - RW – 8 bits - [PM_Reg: 1Dh]
Field Name Bits Default Description
MouseKbMonitorStatus 3 - Mouse/keyboard status bit; write 1’b1 to clear the status bit
ProgramIo3Status 4 - Programmable IO 3 status bit; write 1’b1 to clear the status
bit
ProgramIo2Status 5 - Programmable IO 2 status bit; write 1’b1 to clear the status
bit
ProgramIo1Status 6 - Programmable IO 1 status bit; write 1’b1 to clear the status
bit
ProgramIo0Status
7 - Programmable IO 0 status bit; write 1’b1 to clear the status
bit
IOMonitorStatus register
InactiveTmrEventEnable4 - RW – 8 bits - [PM_Reg: 1Eh]
Field Name Bits Default Description
AD_LIB_Timer1Enable 0 0b Enables Timer1 reload on AD_LIB inactivity
MIDI_Timer1Enable 1 0b Enables Timer1 reload on MIDI inactivity
Audio_Timer1Enable 2 0b Enables Timer1 reload on Audio inactivity
Keyboard_Time1Enable 3 0b Enables Timer1 reload on Keyboard/Mouse port inactivity
PIO3_Timer1Enable 4 0b Enables Timer1 reload on PIO3 port inactivity
PIO2_Timer1Enable 5 0b Enables Timer1 reload on PIO2 port inactivity
PIO1_Timer1Enable 6 0b Enables Timer1 reload on PIO1 port inactivity
PIO0_Timer1Enable 7 0b Enables Timer1 reload on PIO0 port inactivity
InactiveTmrEventEnable4 register.
AcpiPm1EvtBlkLo - RW – 8 bits - [PM_Reg: 20h]
Field Name Bits Default Description
Reserved 1:0 00b
AcpiPm1EvtBlkLo 7:2 00h These bits define the least significant byte of the 16 bit I/O
range base address of the ACPI power management Event
Block. Bit 2 corresponds to Addr[2] and bit 7 corresponds to
Addr[7].
AcpiPm1EvtBlkLo register.
AcpiPm1EvtBlkHi - RW – 8 bits - [PM_Reg: 21h]
Field Name Bits Default Description
AcpiPm1EvtBlkHi 7:0 00h These bits define the most significant byte of the 16 bit I/O
range base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiPm1EvtBlkHi register.
AcpiPm1CntBlkLo - RW – 8 bits - [PM_Reg: 22h]
Field Name Bits Default Description
Reserved 0 0b
AcpiPm1CntBlkLo 7:1 00h These bits define the least significant byte of the 16 bit I/O
base address of the ACPI power management Control block.
Bit 1 corresponds to Addr[1] and bit 7 corresponds to Addr[7].
AcpiPm1CntBlkLo register.
AcpiPm1CntBlkHi - RW – 8 bits - [PM_Reg: 23h]
Field Name Bits Default Description
AcpiPm1CntBlkHi 7:0 00h These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].