Altera SDI II MegaCore User Manual
Sdi ii ip core user guide
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Table of contents
Document Outline
- SDI II IP Core User Guide
- Contents
- 1. SDI II IP Core Quick Reference
- 2. SDI II IP Core Overview
- 3. SDI II IP Core Getting Started
- Installation and Licensing
- Design Walkthrough
- Compiling the SDI II IP Core Design
- Programming an FPGA Device
- Design Reference
- SDI II IP Core Parameters
- SDI II IP Core Component Files
- Design Examples
- Video Pattern Generator Signals
- Transceiver Reconfiguration Controller Signals
- Reconfiguration Management Parameters
- Reconfiguration Router Signals
- 4. SDI II IP Core Functional Description
- Protocol
- Transceiver
- Submodules
- Insert Line
- Insert/Check CRC
- Insert Payload ID
- Match TRS
- Scrambler
- TX Sample
- Clock Enable Generator
- RX Sample
- Detect Video Standard
- Detect 1 and 1/1.001 Rates
- Transceiver Controller
- Descrambler
- TRS Aligner
- 3Gb Demux
- Extract Line
- Extract Payload ID
- Detect Format
- Sync Streams
- Convert SD Bits
- Insert Sync Bits
- Clocking Scheme
- SDI II IP Core Signals
- A. Additional Information