Sdi ii ip core component files, Design examples, Design examples for arria 10 devices – Altera SDI II MegaCore User Manual

Page 24: Sdi ii ip core component files -9, Design examples -9

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SDI II IP Core Component Files

Table 3-3: Generated Files

Table below describes the generated files and other files that might be in your project directory. The names and

types of files vary depending on whether you create your design with VHDL or Verilog HDL.

Extension

Description

<variation name>

.v

or

.sv

An IP core variation file, which defines a Verilog HDL description of the

custom IP core. Instantiate the entity defined by this file inside your design.

Include this file when compiling your design in the Quartus II software.

<variation name>

.sdc

Contains timing constraints for your SDI variation.

<variation name>

.qip

Contains Quartus II project information for your IP core variations.

<variation name>

.tcl

Tcl script file to run in Quartus II software.

Design Examples

Each design example provided with the SDI II IP core is synthesizable.

Design Examples for Arria 10 Devices

The figure below illustrates the generated design example entity and simulation testbench for Arria 10

devices. This design example consists of two SDI channels, a video pattern generator, a reconfiguration

controller, and a loopback path.
The IP core configures the device under test (DUT) block according to your parameterization. For

example, if you choose to generate an SDI RX, the software instantiates an SDI TX block to serve as a

video source.
The loopback block (SDI duplex) is always instantiated in the design example for parallel loopback

demonstrations.
The PHY adapter in the generated example design is not included in the figure below so that you can

observe how the signals are physically connected without the adapter. You may bypass the adapter in your

own design to make the design simpler.
For Arria 10 devices, the transceiver is no longer wrapped inside the IP core, and the TX PLL is no longer

wrapped inside the Transceiver PHY. You must generate these blocks separately in the example design.

UG-01125

2015.05.04

SDI II IP Core Component Files

3-9

SDI II IP Core Getting Started

Altera Corporation

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